Home
last modified time | relevance | path

Searched refs:CLK_SCLK_UART2 (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A Dexynos5410.h24 #define CLK_SCLK_UART2 130 macro
H A Dexynos5250.h45 #define CLK_SCLK_UART2 148 macro
H A Dexynos7-clk.h39 #define CLK_SCLK_UART2 5 macro
H A Dexynos4.h66 #define CLK_SCLK_UART2 153 macro
H A Dexynos5420.h31 #define CLK_SCLK_UART2 130 macro
H A Dexynos3250.h256 #define CLK_SCLK_UART2 248 macro
H A Dexynos5433.h429 #define CLK_SCLK_UART2 34 macro
/linux-6.15/drivers/clk/samsung/
H A Dclk-exynos5410.c217 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
H A Dclk-exynos5250.c499 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
H A Dclk-exynos3250.c566 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
H A Dclk-exynos7.c360 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
H A Dclk-exynos5420.c987 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
H A Dclk-exynos4.c785 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
H A Dclk-exynos5433.c1738 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
/linux-6.15/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
H A Dexynos3250.dtsi705 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
H A Dexynos4.dtsi474 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
H A Dexynos5250.dtsi1204 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
H A Dexynos5420.dtsi1327 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
/linux-6.15/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi223 <&clock_top0 CLK_SCLK_UART2>,
H A Dexynos5433.dtsi1448 <&cmu_peric CLK_SCLK_UART2>;