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Searched refs:CLK_SCLK_UART1 (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A Dexynos5410.h23 #define CLK_SCLK_UART1 129 macro
H A Dexynos5250.h44 #define CLK_SCLK_UART1 147 macro
H A Dexynos7-clk.h38 #define CLK_SCLK_UART1 4 macro
H A Dexynos4.h65 #define CLK_SCLK_UART1 152 macro
H A Dexynos5420.h30 #define CLK_SCLK_UART1 129 macro
H A Dexynos3250.h254 #define CLK_SCLK_UART1 246 macro
H A Dexynos5433.h430 #define CLK_SCLK_UART1 35 macro
/linux-6.15/drivers/clk/samsung/
H A Dclk-exynos5410.c215 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
H A Dclk-exynos5250.c497 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
H A Dclk-exynos3250.c568 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
H A Dclk-exynos7.c362 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
H A Dclk-exynos5420.c985 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
H A Dclk-exynos4.c783 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
H A Dclk-exynos5433.c1741 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
/linux-6.15/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
H A Dexynos3250.dtsi694 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
H A Dexynos4.dtsi463 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
H A Dexynos5250.dtsi1197 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
H A Dexynos5420.dtsi1320 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
/linux-6.15/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi222 <&clock_top0 CLK_SCLK_UART1>,
H A Dexynos5433.dtsi1436 <&cmu_peric CLK_SCLK_UART1>;