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Searched refs:CLK_MCT (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml173 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
193 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
214 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
234 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
/linux-6.15/include/dt-bindings/clock/
H A Dexynos5410.h50 #define CLK_MCT 315 macro
H A Dexynos5250.h139 #define CLK_MCT 335 macro
H A Dexynos4.h182 #define CLK_MCT 344 macro
H A Dexynos5420.h108 #define CLK_MCT 315 macro
H A Dexynos3250.h153 #define CLK_MCT 147 macro
/linux-6.15/drivers/clk/samsung/
H A Dclk-exynos5410.c168 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
H A Dclk-exynos4.c949 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
989 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
H A Dclk-exynos5250.c629 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
H A Dclk-exynos3250.c481 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
H A Dclk-exynos5420.c1127 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
/linux-6.15/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi319 clocks = <&fin_pll>, <&clock CLK_MCT>;
H A Dexynos4210.dtsi286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
H A Dexynos4x12.dtsi299 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
H A Dexynos3250.dtsi455 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
H A Dexynos5250.dtsi247 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
H A Dexynos5420.dtsi1291 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;