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Searched refs:CLKID_MPLL2_DIV (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A Damlogic,s4-pll-clkc.h38 #define CLKID_MPLL2_DIV 28 macro
H A Daxg-clkc.h78 #define CLKID_MPLL2_DIV 67 macro
H A Dgxbb-clkc.h152 #define CLKID_MPLL2_DIV 144 macro
H A Dmeson8b-clkc.h105 #define CLKID_MPLL2_DIV 98 macro
H A Dg12a-clkc.h82 #define CLKID_MPLL2_DIV 71 macro
/linux-6.15/drivers/clk/meson/
H A Ds4-pll.c764 [CLKID_MPLL2_DIV] = &s4_mpll2_div.hw,
H A Dmeson8b.c2869 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
3073 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
3288 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
H A Dgxbb.c2871 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
3078 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
H A Dg12a.c4459 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4686 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4954 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
H A Daxg.c1957 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,