Searched refs:CLK1_CLK2_BYPASS_CNTL (Results 1 – 6 of 6) sorted by relevance
58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass member78 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass member94 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass member210 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass member
185 CLK_SR_DCN35(CLK1_CLK2_BYPASS_CNTL), \291 uint32_t CLK1_CLK2_BYPASS_CNTL; member
298 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); in rn_dump_clk_registers_internal()331 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; in rn_dump_clk_registers()419 internal.CLK1_CLK2_BYPASS_CNTL); in rn_dump_clk_registers()
230 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL); in vg_dump_clk_registers_internal()263 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; in vg_dump_clk_registers()351 internal.CLK1_CLK2_BYPASS_CNTL); in vg_dump_clk_registers()
770 REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source); in dcn314_read_ss_info_from_lut()
728 clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK; in dcn35_read_ss_info_from_lut()