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Searched refs:CLK (Results 1 – 25 of 74) sorted by relevance

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/linux-6.15/arch/arm/mach-omap1/
H A Dclock_data.c607 CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
628 CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
629 CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
634 CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
635 CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
641 CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
643 CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
651 CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
653 CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
[all …]
H A Dclock.h25 #define CLK(dev, con, ck, cp) \ macro
/linux-6.15/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c17 #define CLK 0 macro
131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
144 regmap_write(regmap, 0x32, val[CLK]); in dphy_set_timing_reg()
150 regmap_write(regmap, 0x91, val[CLK]); in dphy_set_timing_reg()
157 regmap_write(regmap, 0x33, val[CLK]); in dphy_set_timing_reg()
163 regmap_write(regmap, 0x92, val[CLK]); in dphy_set_timing_reg()
170 regmap_write(regmap, 0x34, val[CLK]); in dphy_set_timing_reg()
239 val[DATA] = val[CLK]; in dphy_timing_config()
276 val[DATA] = val[CLK]; in dphy_timing_config()
[all …]
/linux-6.15/arch/arm/boot/dts/st/
H A Dste-dbx5x0-pinctrl.dtsi267 pins = "GPIO23_AA4"; /* CLK */
300 pins = "GPIO23_AA4"; /* CLK */
315 pins = "GPIO23_AA4"; /* CLK */
341 pins = "GPIO23_AA4"; /* CLK */
355 pins = "GPIO208_AH16"; /* CLK */
375 pins = "GPIO208_AH16"; /* CLK */
396 pins = "GPIO208_AH16"; /* CLK */
435 pins = "GPIO128_A5"; /* CLK */
464 pins = "GPIO128_A5"; /* CLK */
484 pins = "GPIO128_A5"; /* CLK */
[all …]
H A Dste-href-family-pinctrl.dtsi29 "GPIO217_AH12"; /* CLK */
49 pins = "GPIO217_AH12"; /* CLK */
66 pins = "GPIO217_AH12"; /* CLK */
H A Dstm32f7-pinctrl.dtsi241 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
254 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
272 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
283 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
296 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
314 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
/linux-6.15/Documentation/devicetree/bindings/display/ti/
H A Dti,omap5-dss.txt77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
99 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,omap4-dss.txt96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
118 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,dra7-dss.txt73 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
H A Dti,omap3-dss.txt86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/linux-6.15/Documentation/iio/
H A Dad7625.rst51 | CLK+/CLK- |<xxxxxxx| CLK & CLK_GATE |
/linux-6.15/drivers/gpu/drm/amd/display/dc/gpio/
H A Dddc_regs.h158 DDC_REG_LIST(CLK, id)\
168 DDC_VGA_REG_LIST(CLK)\
187 DDC_REG_LIST_DCN2(CLK, id)\
/linux-6.15/Documentation/devicetree/bindings/media/
H A Drenesas,drif.yaml18 | |-----SCK------->|CLK |
26 CLK & SYNC. Each internal channel has its own dedicated resources like
31 The internal channels sharing the CLK & SYNC are tied together by their
162 # | |-----SCK------->|CLK |
219 # | |-----SCK------->|CLK |
/linux-6.15/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-khadas-vim.dts189 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
198 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
201 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
H A Dmeson-gxbb-nanopi-k2.dts266 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
285 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
288 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
/linux-6.15/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u11-smarc-du-adv7513.dtso59 pinmux = <RZG2L_PORT_PINMUX(11, 3, 6)>; /* CLK */
/linux-6.15/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad7625.yaml43 The clock connected to the CLK pins, gated by the clk_gate PWM.
49 - description: PWM that gates the clock connected to the ADC's CLK input.
H A Dti,ads1298.yaml40 description: Optional 2.048 MHz external source clock on CLK pin
/linux-6.15/arch/arm/boot/dts/allwinner/
H A Dsun8i-h2-plus-bananapi-m2-zero.dts234 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
241 "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
H A Dsun7i-a20-bananapi.dts229 "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3",
246 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
/linux-6.15/arch/arm64/boot/dts/qcom/
H A Dsm8750.dtsi2246 /* MISO, MOSI, CLK */
2261 /* MISO, MOSI, CLK */
2276 /* MISO, MOSI, CLK */
2291 /* MISO, MOSI, CLK */
2306 /* MISO, MOSI, CLK */
2321 /* MISO, MOSI, CLK */
2336 /* MISO, MOSI, CLK */
2351 /* MISO, MOSI, CLK */
2366 /* MISO, MOSI, CLK */
2381 /* MISO, MOSI, CLK */
[all …]
/linux-6.15/drivers/pinctrl/
H A Dpinctrl-th1520.c182 TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0),
185 TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0),
265 TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0),
266 TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0),
267 TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0),
268 TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0),
/linux-6.15/Documentation/devicetree/bindings/hwmon/
H A Dgmt,g762.yaml37 description: a fixed clock providing input clock frequency on CLK
/linux-6.15/Documentation/devicetree/bindings/sound/
H A Dmicrochip,sama7g5-pdmc.yaml52 or falling) of the CLK line. A microphone is represented as a pair of DS
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Drenesas,rzv2h-cpg.yaml47 used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the

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