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Searched refs:CCI_REG8 (Results 1 – 25 of 27) sorted by relevance

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/linux-6.15/drivers/media/i2c/
H A Dov64a40.c152 { CCI_REG8(0x0103), 0x01 }, { CCI_REG8(0x0301), 0x88 },
153 { CCI_REG8(0x0304), 0x00 }, { CCI_REG8(0x0305), 0x96 },
154 { CCI_REG8(0x0306), 0x03 }, { CCI_REG8(0x0307), 0x00 },
155 { CCI_REG8(0x0345), 0x2c }, { CCI_REG8(0x034a), 0x02 },
156 { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x0350), 0xc0 },
157 { CCI_REG8(0x0360), 0x09 }, { CCI_REG8(0x3012), 0x31 },
158 { CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3017), 0xf0 },
159 { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 },
160 { CCI_REG8(0x3022), 0xf0 }, { CCI_REG8(0x3400), 0x08 },
161 { CCI_REG8(0x3608), 0x41 }, { CCI_REG8(0x3421), 0x02 },
[all …]
H A Dgc2145.c135 {CCI_REG8(0x18), 0x22}, {CCI_REG8(0x19), 0x0e}, {CCI_REG8(0x1a), 0x01},
136 {CCI_REG8(0x1b), 0x4b}, {CCI_REG8(0x1c), 0x07}, {CCI_REG8(0x1d), 0x10},
137 {CCI_REG8(0x1e), 0x88}, {CCI_REG8(0x1f), 0x78}, {CCI_REG8(0x20), 0x03},
138 {CCI_REG8(0x21), 0x40}, {CCI_REG8(0x22), 0xa0}, {CCI_REG8(0x24), 0x16},
139 {CCI_REG8(0x25), 0x01}, {CCI_REG8(0x26), 0x10}, {CCI_REG8(0x2d), 0x60},
140 {CCI_REG8(0x30), 0x01}, {CCI_REG8(0x31), 0x90}, {CCI_REG8(0x33), 0x06},
143 {CCI_REG8(0x80), 0x7f}, {CCI_REG8(0x81), 0x26}, {CCI_REG8(0x82), 0xfa},
144 {CCI_REG8(0x83), 0x00}, {CCI_REG8(0x84), 0x02}, {CCI_REG8(0x86), 0x02},
147 {CCI_REG8(0x85), 0x08}, {CCI_REG8(0x8a), 0x00}, {CCI_REG8(0x8b), 0x00},
149 {CCI_REG8(0xc3), 0x00}, {CCI_REG8(0xc4), 0x80}, {CCI_REG8(0xc5), 0x90},
[all …]
H A Dgc05a2.c116 { CCI_REG8(0x0135), 0x01 },
117 { CCI_REG8(0x0084), 0x21 },
118 { CCI_REG8(0x0d05), 0xcc },
119 { CCI_REG8(0x0218), 0x00 },
120 { CCI_REG8(0x005e), 0x48 },
121 { CCI_REG8(0x0d06), 0x01 },
122 { CCI_REG8(0x0007), 0x16 },
123 { CCI_REG8(0x0101), 0x00 },
126 { CCI_REG8(0x0342), 0x07 },
127 { CCI_REG8(0x0343), 0x28 },
[all …]
H A Dgc08a3.c113 { CCI_REG8(0x0336), 0x70 },
114 { CCI_REG8(0x0383), 0xbb },
115 { CCI_REG8(0x0344), 0x00 },
116 { CCI_REG8(0x0345), 0x06 },
117 { CCI_REG8(0x0346), 0x00 },
118 { CCI_REG8(0x0347), 0x04 },
119 { CCI_REG8(0x0348), 0x0c },
120 { CCI_REG8(0x0349), 0xd0 },
121 { CCI_REG8(0x034a), 0x09 },
122 { CCI_REG8(0x034b), 0x9c },
[all …]
H A Dgc0308.c25 #define GC0308_CHIP_ID CCI_REG8(0x000)
26 #define GC0308_HBLANK CCI_REG8(0x001)
27 #define GC0308_VBLANK CCI_REG8(0x002)
35 #define GC0308_VB_HB CCI_REG8(0x00f)
36 #define GC0308_RSH_WIDTH CCI_REG8(0x010)
37 #define GC0308_TSP_WIDTH CCI_REG8(0x011)
47 #define GC0308_VREF_V25 CCI_REG8(0x01d)
48 #define GC0308_ADC_R CCI_REG8(0x01e)
49 #define GC0308_PAD_DRV CCI_REG8(0x01f)
55 #define GC0308_AAAA_EN CCI_REG8(0x022)
[all …]
H A Dov5693.c176 {CCI_REG8(0x3016), 0xf0},
177 {CCI_REG8(0x3017), 0xf0},
178 {CCI_REG8(0x3018), 0xf0},
179 {CCI_REG8(0x3022), 0x01},
180 {CCI_REG8(0x3028), 0x44},
181 {CCI_REG8(0x3098), 0x02},
182 {CCI_REG8(0x3099), 0x19},
183 {CCI_REG8(0x309a), 0x02},
184 {CCI_REG8(0x309b), 0x01},
185 {CCI_REG8(0x309c), 0x00},
[all …]
H A Dimx214.c288 { CCI_REG8(0x3000), 0x35 },
289 { CCI_REG8(0x3054), 0x01 },
290 { CCI_REG8(0x305C), 0x11 },
312 { CCI_REG8(0x3A03), 0x09 },
313 { CCI_REG8(0x3A04), 0x50 },
314 { CCI_REG8(0x3A05), 0x01 },
319 { CCI_REG8(0x30B4), 0x00 },
321 { CCI_REG8(0x3A02), 0xFF },
323 { CCI_REG8(0x3011), 0x00 },
328 { CCI_REG8(0x4170), 0x00 },
[all …]
H A Dimx335.c266 { CCI_REG8(0x3288), 0x21 },
267 { CCI_REG8(0x328a), 0x02 },
268 { CCI_REG8(0x3414), 0x05 },
269 { CCI_REG8(0x3416), 0x18 },
270 { CCI_REG8(0x3648), 0x01 },
271 { CCI_REG8(0x364a), 0x04 },
272 { CCI_REG8(0x364c), 0x04 },
273 { CCI_REG8(0x3678), 0x01 },
274 { CCI_REG8(0x367c), 0x31 },
275 { CCI_REG8(0x367e), 0x31 },
[all …]
H A Dov4689.c171 { CCI_REG8(0x3603), 0x40 },
172 { CCI_REG8(0x3604), 0x02 },
173 { CCI_REG8(0x3609), 0x12 },
174 { CCI_REG8(0x360c), 0x08 },
175 { CCI_REG8(0x360f), 0xe5 },
176 { CCI_REG8(0x3608), 0x8f },
177 { CCI_REG8(0x3611), 0x00 },
178 { CCI_REG8(0x3613), 0xf7 },
179 { CCI_REG8(0x3616), 0x58 },
180 { CCI_REG8(0x3619), 0x99 },
[all …]
H A Dimx290.c273 { CCI_REG8(0x3012), 0x64 },
274 { CCI_REG8(0x3013), 0x00 },
278 { CCI_REG8(0x300f), 0x00 },
279 { CCI_REG8(0x3010), 0x21 },
280 { CCI_REG8(0x3011), 0x00 },
281 { CCI_REG8(0x3016), 0x09 },
282 { CCI_REG8(0x3070), 0x02 },
283 { CCI_REG8(0x3071), 0x11 },
284 { CCI_REG8(0x309b), 0x10 },
285 { CCI_REG8(0x309c), 0x22 },
[all …]
H A Dimx415.c590 { CCI_REG8(0x32D4), 0x21 },
591 { CCI_REG8(0x32EC), 0xA1 },
592 { CCI_REG8(0x3452), 0x7F },
593 { CCI_REG8(0x3453), 0x03 },
594 { CCI_REG8(0x358A), 0x04 },
595 { CCI_REG8(0x35A1), 0x02 },
596 { CCI_REG8(0x36BC), 0x0C },
597 { CCI_REG8(0x36CC), 0x53 },
598 { CCI_REG8(0x36CD), 0x00 },
599 { CCI_REG8(0x36CE), 0x3C },
[all …]
H A Dimx258.c318 { CCI_REG8(0x3051), 0x00 },
319 { CCI_REG8(0x6B11), 0xCF },
320 { CCI_REG8(0x7FF0), 0x08 },
321 { CCI_REG8(0x7FF1), 0x0F },
322 { CCI_REG8(0x7FF2), 0x08 },
323 { CCI_REG8(0x7FF3), 0x1B },
324 { CCI_REG8(0x7FF4), 0x23 },
325 { CCI_REG8(0x7FF5), 0x60 },
326 { CCI_REG8(0x7FF6), 0x00 },
327 { CCI_REG8(0x7FF7), 0x01 },
[all …]
H A Dimx219.c164 { CCI_REG8(0x30eb), 0x05 },
165 { CCI_REG8(0x30eb), 0x0c },
166 { CCI_REG8(0x300a), 0xff },
167 { CCI_REG8(0x300b), 0xff },
168 { CCI_REG8(0x30eb), 0x05 },
169 { CCI_REG8(0x30eb), 0x09 },
172 { CCI_REG8(0x455e), 0x00 },
173 { CCI_REG8(0x471e), 0x4b },
174 { CCI_REG8(0x4767), 0x0f },
175 { CCI_REG8(0x4750), 0x14 },
[all …]
H A Dimx283.c39 #define IMX283_REG_CHIP_ID CCI_REG8(0x3000)
42 #define IMX283_REG_STANDBY CCI_REG8(0x3000)
50 #define IMX283_REG_CLAMP CCI_REG8(0x3001)
56 #define IMX283_REG_MDSEL1 CCI_REG8(0x3004)
57 #define IMX283_REG_MDSEL2 CCI_REG8(0x3005)
58 #define IMX283_REG_MDSEL3 CCI_REG8(0x3006)
60 #define IMX283_REG_MDSEL4 CCI_REG8(0x3007)
82 #define IMX283_REG_TLPX CCI_REG8(0x3026)
131 #define IMX283_REG_XMSTA CCI_REG8(0x3105)
139 #define IMX283_REG_STBPL CCI_REG8(0x320b)
[all …]
H A Dmt9m114.c83 #define MT9M114_CCM_DELTA_GAIN CCI_REG8(0xb42a)
116 #define MT9M114_CAM_MODE_SELECT CCI_REG8(0xc84c)
134 #define MT9M114_CAM_CROP_CROPMODE CCI_REG8(0xc85c)
170 #define MT9M114_CAM_AET_AEMODE CCI_REG8(0xc878)
207 #define MT9M114_CAM_AWB_AWBMODE CCI_REG8(0xc909)
210 #define MT9M114_CAM_AWB_K_R_L CCI_REG8(0xc90c)
211 #define MT9M114_CAM_AWB_K_G_L CCI_REG8(0xc90d)
212 #define MT9M114_CAM_AWB_K_B_L CCI_REG8(0xc90e)
213 #define MT9M114_CAM_AWB_K_R_R CCI_REG8(0xc90f)
214 #define MT9M114_CAM_AWB_K_G_R CCI_REG8(0xc910)
[all …]
H A Dmax96717.c33 #define MAX96717_REG3 CCI_REG8(0x3)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
43 #define MAX96717_VIDEO_TX0 CCI_REG8(0x110)
45 #define MAX96717_VIDEO_TX2 CCI_REG8(0x112)
83 #define MAX96717_FRONTOP0 CCI_REG8(0x308)
87 #define MAX96717_MIPI_RX1 CCI_REG8(0x331)
99 #define MAX96717_MIPI_RX_EXT11 CCI_REG8(0x383)
[all …]
H A Dmax96714.c31 #define MAX96714_REG13 CCI_REG8(0x0d)
32 #define MAX96714_DEV_REV CCI_REG8(0x0e)
34 #define MAX96714_LINK_LOCK CCI_REG8(0x13)
36 #define MAX96714_IO_CHK0 CCI_REG8(0x38)
39 #define MAX96714_VIDEO_RX8 CCI_REG8(0x11a)
43 #define MAX96714_PATGEN_0 CCI_REG8(0x240)
44 #define MAX96714_PATGEN_1 CCI_REG8(0x241)
57 #define MAX96714_PATGEN_GRAD_INC CCI_REG8(0x25d)
60 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264)
61 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265)
[all …]
H A Dthp7312.c38 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001)
46 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c)
73 #define THP7312_REG_WB_MODE CCI_REG8(0xf039)
77 #define THP7312_REG_AF_CONTROL CCI_REG8(0xf040)
81 #define THP7312_REG_AF_SETTING CCI_REG8(0xf041)
88 #define THP7312_REG_AF_SUPPORT CCI_REG8(0xf043)
91 #define THP7312_REG_SATURATION CCI_REG8(0xf052)
92 #define THP7312_REG_SHARPNESS CCI_REG8(0xf053)
93 #define THP7312_REG_BRIGHTNESS CCI_REG8(0xf056)
94 #define THP7312_REG_CONTRAST CCI_REG8(0xf057)
[all …]
H A Dst-mipid02.c28 #define MIPID02_CLK_LANE_WR_REG1 CCI_REG8(0x01)
29 #define MIPID02_CLK_LANE_REG1 CCI_REG8(0x02)
30 #define MIPID02_CLK_LANE_REG3 CCI_REG8(0x04)
31 #define MIPID02_DATA_LANE0_REG1 CCI_REG8(0x05)
32 #define MIPID02_DATA_LANE0_REG2 CCI_REG8(0x06)
33 #define MIPID02_DATA_LANE1_REG1 CCI_REG8(0x09)
34 #define MIPID02_DATA_LANE1_REG2 CCI_REG8(0x0a)
35 #define MIPID02_MODE_REG1 CCI_REG8(0x14)
36 #define MIPID02_MODE_REG2 CCI_REG8(0x15)
37 #define MIPID02_DATA_ID_RREG CCI_REG8(0x17)
[all …]
H A Dvgxy61.c36 #define VGXY61_REG_SYSTEM_FSM CCI_REG8(0x0020)
39 #define VGXY61_REG_NVM CCI_REG8(0x0023)
41 #define VGXY61_REG_STBY CCI_REG8(0x0201)
44 #define VGXY61_REG_STREAMING CCI_REG8(0x0202)
51 #define VGXY61_REG_GPIO_0_CTRL CCI_REG8(0x0236)
52 #define VGXY61_REG_GPIO_1_CTRL CCI_REG8(0x0237)
53 #define VGXY61_REG_GPIO_2_CTRL CCI_REG8(0x0238)
54 #define VGXY61_REG_GPIO_3_CTRL CCI_REG8(0x0239)
57 #define VGXY61_REG_ORIENTATION CCI_REG8(0x0302)
58 #define VGXY61_REG_VT_CTRL CCI_REG8(0x0304)
[all …]
H A Ddw9719.c26 #define DW9719_INFO CCI_REG8(0)
30 #define DW9719_CONTROL CCI_REG8(2)
40 #define DW9719_MODE CCI_REG8(6)
45 #define DW9719_VCM_FREQ CCI_REG8(7)
49 #define DW9761_VCM_PRELOAD CCI_REG8(8)
H A Dalvium-csi2.h23 #define REG_BCRM_V4L2_8BIT(n) (REG_BCRM_V4L2 | CCI_REG8(n))
185 #define REG_BCRM_HEARTBEAT_RW CCI_REG8(0x021f)
188 #define REG_GENCP_CHANGEMODE_W CCI_REG8(0x021c)
189 #define REG_GENCP_CURRENTMODE_R CCI_REG8(0x021d)
190 #define REG_GENCP_IN_HANDSHAKE_RW CCI_REG8(0x001c)
H A Dov2680.c33 #define OV2680_REG_STREAM_CTRL CCI_REG8(0x0100)
34 #define OV2680_REG_SOFT_RESET CCI_REG8(0x0103)
37 #define OV2680_REG_SC_CMMN_SUB_ID CCI_REG8(0x302a)
41 #define OV2680_REG_R_MANUAL CCI_REG8(0x3503)
44 #define OV2680_REG_SENSOR_CTRL_0A CCI_REG8(0x370a)
56 #define OV2680_REG_X_INC CCI_REG8(0x3814)
57 #define OV2680_REG_Y_INC CCI_REG8(0x3815)
58 #define OV2680_REG_FORMAT1 CCI_REG8(0x3820)
59 #define OV2680_REG_FORMAT2 CCI_REG8(0x3821)
61 #define OV2680_REG_ISP_CTRL00 CCI_REG8(0x5080)
/linux-6.15/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
54 #define SMIAPP_REG_U8_MODE_SELECT CCI_REG8(0x0100)
77 #define SMIAPP_REG_U8_GAIN_MODE CCI_REG8(0x0120)
133 #define SMIAPP_REG_U8_TCLK_POST CCI_REG8(0x0800)
136 #define SMIAPP_REG_U8_THS_TRAIL CCI_REG8(0x0803)
[all …]
H A Dccs-regs.h22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
184 #define CCS_R_HDR_MODE CCI_REG8(0x0220)
210 #define CCS_R_PLL_MODE CCI_REG8(0x0310)
271 #define CCS_R_TLPX CCI_REG8(0x0807)
296 #define CCS_R_TWAKEUP CCI_REG8(0x082a)
297 #define CCS_R_TINIT CCI_REG8(0x082b)
405 #define CCS_R_NF_CTRL CCI_REG8(0x0b15)
413 #define CCS_R_OB_DT CCI_REG8(0x0b32)
451 #define CCS_R_PDAF_VC CCI_REG8(0x0d02)
[all …]

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