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Searched refs:CCI_REG16 (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
80 #define SMIAPP_REG_U16_VIO_VOLTAGE CCI_REG16(0x0134)
106 #define SMIAPP_REG_U16_X_ADDR_END CCI_REG16(0x0348)
107 #define SMIAPP_REG_U16_Y_ADDR_END CCI_REG16(0x034a)
110 #define SMIAPP_REG_U16_X_EVEN_INC CCI_REG16(0x0380)
111 #define SMIAPP_REG_U16_X_ODD_INC CCI_REG16(0x0382)
112 #define SMIAPP_REG_U16_Y_EVEN_INC CCI_REG16(0x0384)
113 #define SMIAPP_REG_U16_Y_ODD_INC CCI_REG16(0x0386)
116 #define SMIAPP_REG_U16_SCALE_M CCI_REG16(0x0404)
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H A Dccs-regs.h20 #define CCS_R_MODULE_MODEL_ID CCI_REG16(0x0000)
35 #define CCS_R_DATA_PEDESTAL CCI_REG16(0x0008)
221 #define CCS_R_X_ADDR_END CCI_REG16(0x0348)
222 #define CCS_R_Y_ADDR_END CCI_REG16(0x034a)
233 #define CCS_R_X_EVEN_INC CCI_REG16(0x0380)
234 #define CCS_R_X_ODD_INC CCI_REG16(0x0382)
235 #define CCS_R_Y_EVEN_INC CCI_REG16(0x0384)
242 #define CCS_R_SCALE_M CCI_REG16(0x0404)
243 #define CCS_R_SCALE_N CCI_REG16(0x0406)
283 #define CCS_R_TLPX_EX CCI_REG16(0x0818)
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/linux-6.15/drivers/media/i2c/
H A Dmt9m114.c35 #define MT9M114_CHIP_ID CCI_REG16(0x0000)
58 #define MT9M114_FLASH CCI_REG16(0x3046)
522 { CCI_REG16(0x316a), 0x8270 },
523 { CCI_REG16(0x316c), 0x8270 },
524 { CCI_REG16(0x3ed0), 0x2305 },
525 { CCI_REG16(0x3ed2), 0x77cf },
526 { CCI_REG16(0x316e), 0x8202 },
527 { CCI_REG16(0x3180), 0x87ff },
528 { CCI_REG16(0x30d4), 0x6080 },
529 { CCI_REG16(0xa802), 0x0008 },
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H A Dimx214.c24 #define IMX214_REG_CHIP_ID CCI_REG16(0x0016)
50 #define IMX214_REG_EXPOSURE CCI_REG16(0x0202)
59 #define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204)
92 #define IMX214_REG_EXCK_FREQ CCI_REG16(0x0136)
109 #define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306)
117 #define IMX214_REG_X_ADD_STA CCI_REG16(0x0344)
118 #define IMX214_REG_Y_ADD_STA CCI_REG16(0x0346)
119 #define IMX214_REG_X_ADD_END CCI_REG16(0x0348)
120 #define IMX214_REG_Y_ADD_END CCI_REG16(0x034a)
132 #define IMX214_REG_SCALE_M CCI_REG16(0x0404)
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H A Dimx258.c24 #define IMX258_REG_CHIP_ID CCI_REG16(0x0016)
37 #define IMX258_REG_EXPOSURE CCI_REG16(0x0202)
45 #define IMX258_REG_ANALOG_GAIN CCI_REG16(0x0204)
52 #define IMX258_REG_GR_DIGITAL_GAIN CCI_REG16(0x020e)
53 #define IMX258_REG_R_DIGITAL_GAIN CCI_REG16(0x0210)
54 #define IMX258_REG_B_DIGITAL_GAIN CCI_REG16(0x0212)
55 #define IMX258_REG_GB_DIGITAL_GAIN CCI_REG16(0x0214)
71 #define IMX258_REG_TEST_PATTERN CCI_REG16(0x0600)
110 #define IMX258_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408)
111 #define IMX258_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a)
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H A Dov4689.c27 #define OV4689_REG_CHIP_ID CCI_REG16(0x300a)
34 #define OV4689_REG_GAIN CCI_REG16(0x3508)
38 #define OV4689_REG_DIG_GAIN CCI_REG16(0x352a)
44 #define OV4689_REG_H_CROP_START CCI_REG16(0x3800)
45 #define OV4689_REG_V_CROP_START CCI_REG16(0x3802)
46 #define OV4689_REG_H_CROP_END CCI_REG16(0x3804)
47 #define OV4689_REG_V_CROP_END CCI_REG16(0x3806)
51 #define OV4689_REG_HTS CCI_REG16(0x380c)
55 #define OV4689_REG_VTS CCI_REG16(0x380e)
58 #define OV4689_REG_H_WIN_OFF CCI_REG16(0x3810)
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H A Dimx219.c33 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000)
48 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a)
59 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158)
66 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a)
81 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164)
82 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166)
83 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168)
84 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a)
105 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306)
108 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c)
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H A Dgc2145.c32 #define GC2145_REG_HBLANK CCI_REG16(0x05)
33 #define GC2145_REG_VBLANK CCI_REG16(0x07)
396 {CCI_REG16(0x25), 0x0175},
398 {CCI_REG16(0x27), 0x045f}, {CCI_REG16(0x29), 0x045f},
399 {CCI_REG16(0x2b), 0x045f}, {CCI_REG16(0x2d), 0x045f},
428 {CCI_REG16(0x25), 0x00e6},
430 {CCI_REG16(0x27), 0x02b2}, {CCI_REG16(0x29), 0x02b2},
431 {CCI_REG16(0x2b), 0x02b2}, {CCI_REG16(0x2d), 0x02b2},
460 {CCI_REG16(0x25), 0x00fa},
462 {CCI_REG16(0x27), 0x04e2}, {CCI_REG16(0x29), 0x04e2},
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H A Dov2680.c36 #define OV2680_REG_CHIP_ID CCI_REG16(0x300a)
38 #define OV2680_REG_PLL_MULTIPLIER CCI_REG16(0x3081)
42 #define OV2680_REG_GAIN_PK CCI_REG16(0x350a)
47 #define OV2680_REG_VERTICAL_START CCI_REG16(0x3802)
49 #define OV2680_REG_VERTICAL_END CCI_REG16(0x3806)
52 #define OV2680_REG_TIMING_HTS CCI_REG16(0x380c)
53 #define OV2680_REG_TIMING_VTS CCI_REG16(0x380e)
54 #define OV2680_REG_ISP_X_WIN CCI_REG16(0x3810)
55 #define OV2680_REG_ISP_Y_WIN CCI_REG16(0x3812)
63 #define OV2680_REG_X_WIN CCI_REG16(0x5704)
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H A Dalvium-csi2.h24 #define REG_BCRM_V4L2_16BIT(n) (REG_BCRM_V4L2 | CCI_REG16(n))
29 #define REG_BCRM_MINOR_VERSION_R CCI_REG16(0x0000)
30 #define REG_BCRM_MAJOR_VERSION_R CCI_REG16(0x0002)
31 #define REG_BCRM_REG_ADDR_R CCI_REG16(0x0014)
191 #define REG_GENCP_OUT_SIZE_W CCI_REG16(0x0020)
192 #define REG_GENCP_IN_SIZE_R CCI_REG16(0x0024)
H A Dov5693.c38 #define OV5693_REG_CHIP_ID CCI_REG16(0x300a)
50 #define OV5693_GAIN_CTRL_REG CCI_REG16(0x350a)
58 #define OV5693_MWB_RED_GAIN_REG CCI_REG16(0x3400)
60 #define OV5693_MWB_BLUE_GAIN_REG CCI_REG16(0x3404)
69 #define OV5693_CROP_START_X_REG CCI_REG16(0x3800)
70 #define OV5693_CROP_START_Y_REG CCI_REG16(0x3802)
71 #define OV5693_CROP_END_X_REG CCI_REG16(0x3804)
72 #define OV5693_CROP_END_Y_REG CCI_REG16(0x3806)
73 #define OV5693_OUTPUT_SIZE_X_REG CCI_REG16(0x3808)
76 #define OV5693_TIMING_HTS_REG CCI_REG16(0x380c)
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H A Dgc0308.c28 #define GC0308_EXP CCI_REG16(0x003)
29 #define GC0308_ROW_START CCI_REG16(0x005)
30 #define GC0308_COL_START CCI_REG16(0x007)
31 #define GC0308_WIN_HEIGHT CCI_REG16(0x009)
32 #define GC0308_WIN_WIDTH CCI_REG16(0x00b)
71 #define GC0308_CROP_WIN_HEIGHT CCI_REG16(0x049)
72 #define GC0308_CROP_WIN_WIDTH CCI_REG16(0x04b)
247 #define GC0308_EXP_LVL_1 CCI_REG16(0x0e4)
248 #define GC0308_EXP_LVL_2 CCI_REG16(0x0e6)
249 #define GC0308_EXP_LVL_3 CCI_REG16(0x0e8)
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H A Dlt6911uxe.c22 #define REG_CHIP_ID CCI_REG16(0xe100)
27 #define REG_HALF_H_TOTAL CCI_REG16(0xe088)
28 #define REG_V_TOTAL CCI_REG16(0xe08a)
29 #define REG_HALF_H_ACTIVE CCI_REG16(0xe08c)
30 #define REG_V_ACTIVE CCI_REG16(0xe08e)
H A Dmax96714.c50 #define MAX96714_PATGEN_HS_HIGH CCI_REG16(0x24e)
51 #define MAX96714_PATGEN_HS_LOW CCI_REG16(0x250)
52 #define MAX96714_PATGEN_HS_CNT CCI_REG16(0x252)
54 #define MAX96714_PATGEN_DE_HIGH CCI_REG16(0x257)
55 #define MAX96714_PATGEN_DE_LOW CCI_REG16(0x259)
56 #define MAX96714_PATGEN_DE_CNT CCI_REG16(0x25b)
H A Dgc05a2.c40 #define GC05A2_EXP_REG CCI_REG16(0x0202)
45 #define GC05A2_AGAIN_REG CCI_REG16(0x0204)
50 #define GC05A2_FRAME_LENGTH_REG CCI_REG16(0x0340)
53 #define GC05A2_REG_CHIP_ID CCI_REG16(0x03f0)
178 { CCI_REG16(0x034c), 2592 }, /* Width */
267 { CCI_REG16(0x034c), 1280 }, /* Width */
H A Dmax96717.c56 #define MAX96717_VTX_HS_HIGH CCI_REG16(0x25c)
57 #define MAX96717_VTX_HS_LOW CCI_REG16(0x25e)
58 #define MAX96717_VTX_HS_CNT CCI_REG16(0x260)
60 #define MAX96717_VTX_DE_HIGH CCI_REG16(0x265)
61 #define MAX96717_VTX_DE_LOW CCI_REG16(0x267)
62 #define MAX96717_VTX_DE_CNT CCI_REG16(0x269)
H A Ddw9719.c35 #define DW9719_VCM_CURRENT CCI_REG16(3)
37 #define DW9719_STATUS CCI_REG16(5)
H A Dgc08a3.c40 #define GC08A3_EXP_REG CCI_REG16(0x0202)
45 #define GC08A3_AGAIN_REG CCI_REG16(0x0204)
50 #define GC08A3_FRAME_LENGTH_REG CCI_REG16(0x0340)
53 #define GC08A3_REG_CHIP_ID CCI_REG16(0x03f0)
H A Dov64a40.c41 #define OV64A40_PLL1_MULTIPLIER CCI_REG16(0x0304)
45 #define OV64A40_PLL2_MULTIPLIER CCI_REG16(0x0324)
59 #define OV64A40_REG_MEC_LONG_GAIN CCI_REG16(0x3508)
64 #define OV64A40_REG_TIMING_CTRL0 CCI_REG16(0x3800)
65 #define OV64A40_REG_TIMING_CTRL2 CCI_REG16(0x3802)
66 #define OV64A40_REG_TIMING_CTRL4 CCI_REG16(0x3804)
67 #define OV64A40_REG_TIMING_CTRL6 CCI_REG16(0x3806)
68 #define OV64A40_REG_TIMING_CTRL8 CCI_REG16(0x3808)
69 #define OV64A40_REG_TIMING_CTRLA CCI_REG16(0x380a)
70 #define OV64A40_REG_TIMING_CTRLC CCI_REG16(0x380c)
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H A Dthp7312.c76 #define THP7312_REG_MANUAL_FOCUS_POSITION CCI_REG16(0xf03c)
/linux-6.15/include/media/
H A Dv4l2-cci.h49 #define CCI_REG16(x) ((2 << CCI_REG_WIDTH_SHIFT) | (x)) macro