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Searched refs:CACHE_MODE_1 (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c74 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
106 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
H A Dhandlers.c2261 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c381 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); in gen8_ctx_workarounds_init()
467 wa_masked_en(wal, CACHE_MODE_1, in gen9_ctx_workarounds_init()
783 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); in dg2_ctx_workarounds_init()
831 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); in xelpg_ctx_workarounds_init()
2577 CACHE_MODE_1, in rcs_engine_wa_init()
H A Dgen7_renderclear.c406 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
H A Dintel_gt_regs.h446 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ macro
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_wa.c701 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
722 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h134 #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) macro
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c104 MMIO_D(CACHE_MODE_1); in iterate_generic_mmio()