Searched refs:C10_PLL15_TXCLKDIV_MASK (Results 1 – 3 of 3) sorted by relevance
352 pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) | in intel_snps_hdmi_pll_compute_c10pll()
239 #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) macro
2176 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); in intel_c10pll_dump_hw_state()2735 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()