Searched refs:C10_PLL0_DIV5CLK_EN (Results 1 – 2 of 2) sorted by relevance
337 pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) | in intel_snps_hdmi_pll_compute_c10pll()
224 #define C10_PLL0_DIV5CLK_EN REG_BIT8(2) macro