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Searched refs:BIT_ULL (Results 1 – 25 of 605) sorted by relevance

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/linux-6.15/drivers/gpu/drm/panfrost/
H A Dpanfrost_issues.h142 BIT_ULL(HW_ISSUE_9435))
145 BIT_ULL(HW_ISSUE_6367) | \
146 BIT_ULL(HW_ISSUE_6787) | \
147 BIT_ULL(HW_ISSUE_8408) | \
148 BIT_ULL(HW_ISSUE_9510) | \
158 BIT_ULL(HW_ISSUE_8186) | \
159 BIT_ULL(HW_ISSUE_8245) | \
160 BIT_ULL(HW_ISSUE_8316) | \
167 BIT_ULL(GPUCORE_1619))
182 BIT_ULL(HW_ISSUE_11035))
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H A Dpanfrost_features.h30 BIT_ULL(HW_FEATURE_V4))
39 BIT_ULL(HW_FEATURE_XAFFINITY) | \
53 BIT_ULL(HW_FEATURE_XAFFINITY) | \
57 BIT_ULL(HW_FEATURE_COHERENCY_REG))
62 BIT_ULL(HW_FEATURE_XAFFINITY) | \
67 BIT_ULL(HW_FEATURE_COHERENCY_REG))
74 BIT_ULL(HW_FEATURE_XAFFINITY) | \
80 BIT_ULL(HW_FEATURE_COHERENCY_REG))
85 BIT_ULL(HW_FEATURE_XAFFINITY) | \
99 BIT_ULL(HW_FEATURE_XAFFINITY) | \
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/linux-6.15/arch/mips/include/asm/
H A Dcpu.h360 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
361 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
362 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
363 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
364 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
373 #define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
374 #define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
380 #define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
401 #define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
413 BIT_ULL(54) /* CPU shares FTLB RAM with another */
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/linux-6.15/drivers/mmc/host/
H A Dcavium.h134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
144 #define MIO_EMM_DMA_VAL BIT_ULL(59)
145 #define MIO_EMM_DMA_SECTOR BIT_ULL(58)
148 #define MIO_EMM_DMA_REL_WR BIT_ULL(50)
149 #define MIO_EMM_DMA_RW BIT_ULL(49)
150 #define MIO_EMM_DMA_MULTI BIT_ULL(48)
154 #define MIO_EMM_DMA_CFG_EN BIT_ULL(63)
155 #define MIO_EMM_DMA_CFG_RW BIT_ULL(62)
166 #define MIO_EMM_INT_DMA_ERR BIT_ULL(4)
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/linux-6.15/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
89 #define SPU_CTL_RESET BIT_ULL(15)
141 #define SMU_CTL_RX_IDLE BIT_ULL(0)
142 #define SMU_CTL_TX_IDLE BIT_ULL(1)
144 #define RX_EN BIT_ULL(0)
145 #define TX_EN BIT_ULL(1)
146 #define BCK_EN BIT_ULL(2)
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/linux-6.15/drivers/ras/amd/atl/
H A Ddehash.c67 ctx->ret_addr ^= BIT_ULL(12); in df3_dehash_addr()
81 ctx->ret_addr ^= BIT_ULL(13); in df3_dehash_addr()
155 ctx->ret_addr ^= BIT_ULL(8); in df4_dehash_addr()
174 ctx->ret_addr ^= BIT_ULL(12); in df4_dehash_addr()
188 ctx->ret_addr ^= BIT_ULL(13); in df4_dehash_addr()
202 ctx->ret_addr ^= BIT_ULL(14); in df4_dehash_addr()
248 ctx->ret_addr ^= BIT_ULL(8); in df4p5_dehash_addr()
261 ctx->ret_addr ^= BIT_ULL(9); in df4p5_dehash_addr()
274 ctx->ret_addr ^= BIT_ULL(12); in df4p5_dehash_addr()
287 ctx->ret_addr ^= BIT_ULL(13); in df4p5_dehash_addr()
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/linux-6.15/drivers/iommu/riscv/
H A Diommu-bits.h89 #define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4)
302 #define RISCV_IOMMU_DDTE_V BIT_ULL(0)
335 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0)
339 #define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4)
340 #define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5)
341 #define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6)
344 #define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9)
430 #define RISCV_IOMMU_PC_TA_V BIT_ULL(0)
431 #define RISCV_IOMMU_PC_TA_ENS BIT_ULL(1)
432 #define RISCV_IOMMU_PC_TA_SUM BIT_ULL(2)
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/linux-6.15/arch/loongarch/include/asm/
H A Dcpu.h107 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
108 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
109 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
110 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
111 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
115 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
119 #define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
121 #define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
123 #define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
127 #define LOONGARCH_CPU_PMP BIT_ULL(CPU_FEATURE_PMP)
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/linux-6.15/drivers/infiniband/hw/irdma/
H A Ddefs.h467 #define IRDMA_CQ_EXTCQE BIT_ULL(50)
468 #define IRDMA_OOO_CMPL BIT_ULL(54)
469 #define IRDMA_CQ_ERROR BIT_ULL(55)
470 #define IRDMA_CQ_SQ BIT_ULL(62)
472 #define IRDMA_CQ_VALID BIT_ULL(63)
490 #define IRDMACQ_STAG BIT_ULL(53)
491 #define IRDMACQ_IPV4 BIT_ULL(53)
706 #define IRDMAQPC_IPV4 BIT_ULL(3)
709 #define IRDMAQPC_ISQP1 BIT_ULL(6)
726 #define IRDMAQPC_PMENA BIT_ULL(47)
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H A Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
48 #define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14)
58 #define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11)
59 #define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14)
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/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_gtt_defs.h9 #define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
10 #define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
19 #define XE_PPGTT_PTE_PAT2 BIT_ULL(7)
23 #define XE_PDE_PS_2M BIT_ULL(7)
24 #define XE_PDPE_PS_1G BIT_ULL(7)
25 #define XE_PDE_IPS_64K BIT_ULL(11)
27 #define XE_GGTT_PTE_DM BIT_ULL(1)
30 #define XE_PDE_64K BIT_ULL(6)
31 #define XE_PTE_PS64 BIT_ULL(8)
32 #define XE_PTE_NULL BIT_ULL(9)
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/linux-6.15/drivers/net/ethernet/intel/ice/
H A Dice_flow.h15 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
16 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
18 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
19 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
21 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
22 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
25 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
28 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
42 (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
109 (BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
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/linux-6.15/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
27 #define KOMEDA_ERR_TEMR BIT_ULL(15)
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/linux-6.15/arch/x86/include/asm/
H A Dmce.h15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
64 #define MCI_CONFIG_FRUTEXT BIT_ULL(9)
98 #define MCI_CTL2_CMCI_EN BIT_ULL(30)
145 #define MCE_HANDLED_CEC BIT_ULL(0)
146 #define MCE_HANDLED_UC BIT_ULL(1)
147 #define MCE_HANDLED_EXTLOG BIT_ULL(2)
148 #define MCE_HANDLED_NFIT BIT_ULL(3)
149 #define MCE_HANDLED_EDAC BIT_ULL(4)
150 #define MCE_HANDLED_MCELOG BIT_ULL(5)
158 #define MCE_IN_KERNEL_RECOV BIT_ULL(6)
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/linux-6.15/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_regs_cn9k.h20 #define CN93_VF_RING_OFFSET BIT_ULL(17)
69 #define CN93_VF_R_IN_CTL_IDLE BIT_ULL(28)
71 #define CN93_VF_R_IN_CTL_IS_64B BIT_ULL(24)
72 #define CN93_VF_R_IN_CTL_D_NSR BIT_ULL(8)
73 #define CN93_VF_R_IN_CTL_D_ESR BIT_ULL(6)
74 #define CN93_VF_R_IN_CTL_D_ROR BIT_ULL(5)
75 #define CN93_VF_R_IN_CTL_NSR BIT_ULL(3)
76 #define CN93_VF_R_IN_CTL_ESR BIT_ULL(1)
77 #define CN93_VF_R_IN_CTL_ROR BIT_ULL(0)
143 #define CN93_VF_SDP_R_MBOX_PF_VF_INT_ENAB BIT_ULL(1)
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/linux-6.15/tools/testing/selftests/kvm/include/x86/
H A Dpmu.h28 #define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
29 #define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
32 #define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
39 #define INTEL_RDPMC_METRICS BIT_ULL(29)
40 #define INTEL_RDPMC_FIXED BIT_ULL(30)
41 #define INTEL_RDPMC_FAST BIT_ULL(31)
46 #define FIXED_PMC_KERNEL BIT_ULL(0)
47 #define FIXED_PMC_USER BIT_ULL(1)
48 #define FIXED_PMC_ANYTHREAD BIT_ULL(2)
49 #define FIXED_PMC_ENABLE_PMI BIT_ULL(3)
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/linux-6.15/drivers/vdpa/pds/
H A Ddebugfs.c54 u64 mask = BIT_ULL(i); in print_feature_bits_all()
57 case BIT_ULL(VIRTIO_NET_F_CSUM): in print_feature_bits_all()
66 case BIT_ULL(VIRTIO_NET_F_MTU): in print_feature_bits_all()
69 case BIT_ULL(VIRTIO_NET_F_MAC): in print_feature_bits_all()
99 case BIT_ULL(VIRTIO_NET_F_STATUS): in print_feature_bits_all()
102 case BIT_ULL(VIRTIO_NET_F_CTRL_VQ): in print_feature_bits_all()
117 case BIT_ULL(VIRTIO_NET_F_MQ): in print_feature_bits_all()
126 case BIT_ULL(VIRTIO_NET_F_RSS): in print_feature_bits_all()
141 case BIT_ULL(VIRTIO_F_ANY_LAYOUT): in print_feature_bits_all()
144 case BIT_ULL(VIRTIO_F_VERSION_1): in print_feature_bits_all()
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/linux-6.15/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h764 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
767 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
778 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
779 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
789 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
790 #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
802 #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
804 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
814 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
815 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
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/linux-6.15/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h21 #define RPM_NIX0_RESET BIT_ULL(3)
65 #define RPM_TX_EN BIT_ULL(0)
66 #define RPM_RX_EN BIT_ULL(1)
82 #define RPMX_ONESTEP_ENABLE BIT_ULL(5)
83 #define RPMX_TS_BINARY_MODE BIT_ULL(11)
89 #define RPMX_RSFEC_RX_CAPTURE BIT_ULL(28)
90 #define RPMX_CMD_CLEAR_RX BIT_ULL(30)
91 #define RPMX_CMD_CLEAR_TX BIT_ULL(31)
107 #define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2)
108 #define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1)
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H A Dcgx.h29 #define DATA_PKT_TX_EN BIT_ULL(53)
30 #define DATA_PKT_RX_EN BIT_ULL(54)
34 #define FW_CGX_INT BIT_ULL(1)
36 #define CGX_NIX0_RESET BIT_ULL(2)
37 #define CGX_NIX1_RESET BIT_ULL(3)
38 #define CGX_NSCI_DROP BIT_ULL(9)
45 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
46 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
47 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
48 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
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/linux-6.15/drivers/firmware/efi/
H A Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
33 #define INFO_VALID_IP BIT_ULL(4)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
38 #define CHECK_VALID_PCC BIT_ULL(3)
52 #define CHECK_PCC BIT_ULL(25)
53 #define CHECK_UNCORRECTED BIT_ULL(26)
54 #define CHECK_PRECISE_IP BIT_ULL(27)
56 #define CHECK_OVERFLOW BIT_ULL(29)
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/linux-6.15/include/media/
H A Drc-map.h16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
25 #define RC_PROTO_BIT_NECX BIT_ULL(RC_PROTO_NECX)
26 #define RC_PROTO_BIT_NEC32 BIT_ULL(RC_PROTO_NEC32)
27 #define RC_PROTO_BIT_SANYO BIT_ULL(RC_PROTO_SANYO)
36 #define RC_PROTO_BIT_XMP BIT_ULL(RC_PROTO_XMP)
37 #define RC_PROTO_BIT_CEC BIT_ULL(RC_PROTO_CEC)
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/linux-6.15/drivers/net/ethernet/intel/iavf/
H A Diavf.h307 #define IAVF_FLAG_AQ_ENABLE_QUEUES BIT_ULL(0)
308 #define IAVF_FLAG_AQ_DISABLE_QUEUES BIT_ULL(1)
309 #define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT_ULL(2)
311 #define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT_ULL(4)
314 #define IAVF_FLAG_AQ_MAP_VECTORS BIT_ULL(7)
315 #define IAVF_FLAG_AQ_HANDLE_RESET BIT_ULL(8)
317 #define IAVF_FLAG_AQ_GET_CONFIG BIT_ULL(10)
319 #define IAVF_FLAG_AQ_GET_HENA BIT_ULL(11)
320 #define IAVF_FLAG_AQ_SET_HENA BIT_ULL(12)
321 #define IAVF_FLAG_AQ_SET_RSS_KEY BIT_ULL(13)
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/linux-6.15/drivers/net/ethernet/intel/idpf/
H A Didpf_lan_txrx.h41 (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \
42 BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \
43 BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \
44 BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \
45 BIT_ULL(IDPF_HASH_FRAG_IPV4) | \
46 BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \
47 BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \
48 BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \
49 BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \
50 BIT_ULL(IDPF_HASH_FRAG_IPV6) | \
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/linux-6.15/arch/x86/include/asm/shared/
H A Dtdx.h24 #define TDX_ATTR_DEBUG BIT_ULL(TDX_ATTR_DEBUG_BIT)
28 #define TDX_ATTR_PERF_PROF BIT_ULL(TDX_ATTR_PERF_PROF_BIT)
30 #define TDX_ATTR_PMT_PROF BIT_ULL(TDX_ATTR_PMT_PROF_BIT)
32 #define TDX_ATTR_ICSSD BIT_ULL(TDX_ATTR_ICSSD_BIT)
34 #define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT)
40 #define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT)
42 #define TDX_ATTR_KL BIT_ULL(TDX_ATTR_KL_BIT)
44 #define TDX_ATTR_TPA BIT_ULL(TDX_ATTR_TPA_BIT)
46 #define TDX_ATTR_PERFMON BIT_ULL(TDX_ATTR_PERFMON_BIT)
55 #define TDCS_CONFIG_FLEXIBLE_PENDING_VE BIT_ULL(1)
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