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Searched refs:BAR0 (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/sound/pci/lola/
H A Dlola.c93 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
114 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
311 gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
361 lola_writeb(chip, BAR0, RIRBCTL, 0); in setup_corb_rirb()
362 lola_writeb(chip, BAR0, CORBCTL, 0); in setup_corb_rirb()
367 !lola_readb(chip, BAR0, CORBCTL)) in setup_corb_rirb()
378 lola_writew(chip, BAR0, CORBWP, 0); in setup_corb_rirb()
386 lola_writeb(chip, BAR0, CORBSTS, tmp); in setup_corb_rirb()
397 lola_writew(chip, BAR0, RINTCNT, 1); in setup_corb_rirb()
412 lola_writeb(chip, BAR0, RIRBCTL, 0); in stop_corb_rirb()
[all …]
H A Dlola_proc.c167 readl(chip->bar[BAR0].remap_addr + i)); in lola_proc_regs_read()
H A Dlola.h373 #define BAR0 0 macro
/linux-6.15/Documentation/scsi/
H A Dhptiop.rst11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
14 BAR0 offset Register
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
39 BAR0 offset Register
54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
57 BAR0 offset Register
78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
81 BAR0 offset Register
119 relative to the IOP BAR0.
H A DChangeLog.lpfc1085 CONFIG_PORT uses HBA's view of its BAR0.
/linux-6.15/Documentation/PCI/endpoint/
H A Dpci-vntb-function.rst108 BAR0 Config Region
121 BAR0 Config Region + Scratchpad
H A Dpci-test-function.rst33 This register will be used to test BAR0. A known pattern will be written
34 and read back from MAGIC register to verify BAR0.
H A Dpci-ntb-function.rst239 BAR0 Config Region
261 BAR0 Config Region + Self Scratchpad
277 | BAR0 | | CONFIG REGION | | BAR0 |
293 region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.
305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
H A Dpci-test-howto.rst148 # RUN pci_ep_bar.BAR0.BAR_TEST ...
149 # OK pci_ep_bar.BAR0.BAR_TEST
150 ok 1 pci_ep_bar.BAR0.BAR_TEST
/linux-6.15/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst98 program BAR0 size as 1MB::
106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
109 as BAR0 address then when this device will be connected to a host, it will be
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dpci-ep-bus.yaml43 through BAR0 and another through BAR1, and you don't want the two
/linux-6.15/drivers/ntb/hw/idt/
H A DKconfig21 accepted by a BAR. Note that BAR0 must map PCI configuration space
/linux-6.15/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_pf_device.c1141 u64 BAR0, BAR1; in setup_cn23xx_octeon_pf_device() local
1144 BAR0 = (u64)(data32 & ~0xf); in setup_cn23xx_octeon_pf_device()
1146 BAR0 |= ((u64)data32 << 32); in setup_cn23xx_octeon_pf_device()
1152 if (!BAR0 || !BAR1) { in setup_cn23xx_octeon_pf_device()
1153 if (!BAR0) in setup_cn23xx_octeon_pf_device()
/linux-6.15/tools/testing/selftests/pci_endpoint/
H A Dpci_endpoint_test.c56 FIXTURE_VARIANT_ADD(pci_ep_bar, BAR0) { .barno = 0 }; in FIXTURE_VARIANT_ADD() argument
/linux-6.15/drivers/misc/
H A Dlan966x_pci.dtso56 * map @0xe2000000 (32MB) to BAR0 (CPU)
/linux-6.15/Documentation/networking/device_drivers/ethernet/huawei/
H A Dhinic.rst50 configuration and status BAR0. (hinic_hw_csr.h)
/linux-6.15/Documentation/driver-api/virtio/
H A Dvirtio.rst105 /* Also try modern mode if we can't map BAR0 (no IO space). */
/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1086 /* PF0-6 BAR0 - non-prefetchable memory */
1090 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
1094 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
H A Dimx95.dtsi1834 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
1838 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */
1878 /* EMDIO BAR0 - non-prefetchable memory */
/linux-6.15/Documentation/arch/powerpc/
H A Dpci_iov_resource_on_powernv.rst180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
182 is a BAR0 for one of the VFs. Note that even though the VF BAR
/linux-6.15/Documentation/driver-api/media/drivers/
H A Dcx2341x-devel.rst31 The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
33 address held in BAR0.
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.