| /linux-6.15/tools/testing/selftests/bpf/prog_tests/ |
| H A D | cgroup_attach_override.c | 8 #define BAR "/foo/bar/" macro 55 bar = test__join_cgroup(BAR); in serial_test_cgroup_attach_override() 66 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override() 74 "detach prog from %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override() 84 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override() 98 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override() 103 "attach prog to %s unexpectedly succeeded\n", BAR)) in serial_test_cgroup_attach_override() 108 "detach prog from %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override() 123 "attach prog to %s unexpectedly succeeded\n", BAR)) in serial_test_cgroup_attach_override() 129 "attach prog to %s unexpectedly succeeded\n", BAR)) in serial_test_cgroup_attach_override()
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| /linux-6.15/Documentation/arch/powerpc/ |
| H A D | pci_iov_resource_on_powernv.rst | 173 software uses VF BAR registers in the *PF* SR-IOV Capability to 215 more in the next two sections. For a given VF BAR, we need to 217 position the VF BAR to start at the beginning of a free range of 244 VF(n) BAR space 253 Figure 1.0 Direct map VF(n) BAR space 263 VF(n) BAR space + extra 272 Figure 1.1 Map VF(n) BAR space + extra 285 aligned to the size of an individual VF BAR. 294 of the VF(n) BAR space in the VF BAR. If the PCI core allocates the exact 295 amount of space required for the VF(n) BAR space, the VF BAR value is fixed [all …]
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| H A D | eeh-pci-error-recovery.rst | 95 config space (the base address registers (BAR's), latency timer, 177 It saves the device BAR's and then calls rpaphp_unconfig_pci_adapter(). 183 It then resets the PCI card, reconfigures the device BAR's, and
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| /linux-6.15/Documentation/gpu/rfc/ |
| H A D | i915_small_bar.rst | 2 I915 Small BAR RFC Section 4 Starting from DG2 we will have resizable BAR support for device local-memory(i.e 5 I915_MEMORY_CLASS_DEVICE), but in some cases the final BAR size might still be 14 underneath the device has a small BAR, meaning only some portion of it is CPU 41 1) Error capture is best effort on small BAR systems; if the pages are not
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| /linux-6.15/Documentation/accel/amdxdna/ |
| H A D | amdnpu.rst | 89 * PSP BAR: Expose the AMD PSP (Platform Security Processor) function 90 * SMU BAR: Expose the AMD SMU (System Management Unit) function 91 * SRAM BAR: Expose ring buffers for the mailbox 92 * Mailbox BAR: Expose the mailbox control registers (head, tail and ISR 94 * Public Register BAR: Expose public registers 96 On specific devices, the above-mentioned BAR type might be combined into a 97 single physical PCIe BAR. Or a module might require two physical PCIe BARs to 101 * On AMD Strix Point device, Mailbox and Public Register BARs are on PCIe BAR 102 index 0. The PSP has some registers in PCIe BAR index 0 (Public Register BAR) 103 and PCIe BAR index 4 (PSP BAR). [all …]
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| /linux-6.15/Documentation/devicetree/bindings/pci/ |
| H A D | pci-ep-bus.yaml | 32 - maximum: 5 # The BAR number 40 One node for each BAR used by peripherals contained in the PCI endpoint. 44 peripherals to be able to act on the other BAR. Alternatively, when
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| H A D | cdns-pcie-host.yaml | 27 Set into the no BAR match register to configure the number of least
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| /linux-6.15/drivers/ntb/hw/idt/ |
| H A D | Kconfig | 21 accepted by a BAR. Note that BAR0 must map PCI configuration space 25 BAR settings of peer NT-functions, the BAR setups can't be done over
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| /linux-6.15/Documentation/misc-devices/ |
| H A D | pci-endpoint-test.rst | 15 #) verifying addresses programmed in BAR 31 Tests the BAR. The number of the BAR to be tested
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| /linux-6.15/Documentation/PCI/endpoint/ |
| H A D | pci-ntb-function.rst | 117 the outbound ATU such that transactions to Doorbell BAR will be routed 128 will configure the outbound ATU such that transactions to MW BAR 155 same BAR. The initial portion of the region will have doorbell 166 same BAR. The initial portion of the region will have config region 177 Used to determine the offset within the DB BAR that should be written 233 If one 32-bit BAR is allocated for each of these regions, the scheme would 237 BAR NO CONSTRUCTS USED 247 However if we allocate a separate BAR for each of the regions, there would not 259 BAR NO CONSTRUCTS USED
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| H A D | pci-vntb-function.rst | 106 BAR NO CONSTRUCTS USED 119 BAR NO CONSTRUCTS USED
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| H A D | pci-endpoint.rst | 49 * set_bar: ops to configure the BAR 50 * clear_bar: ops to reset the BAR 101 the BAR. 216 The PCI Function driver can allocate space for a particular BAR using
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| /linux-6.15/Documentation/kbuild/ |
| H A D | kconfig-language.rst | 128 bool "foo" if BAR 129 default y if BAR 133 depends on BAR 151 if FOO depends on BAR that is not set. 177 depends on BAR 202 imply BAR 527 depends on BAR && m 578 depends on BAR || !BAR 581 the combination of FOO=y with BAR=m, or BAR is completely disabled. The BAR 592 def_tristate BAR || !BAR [all …]
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| /linux-6.15/Documentation/translations/zh_CN/PCI/ |
| H A D | acpi-info.rst | 25 发现它们,使用配置访问来发现和识别设备,并读取和测量它们的BAR。然而,如果ACPI为它们 29 ACPI资源描述是通过ACPI命名空间中设备的_CRS对象完成的[2]。_CRS就像一个通用的PCI BAR:
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| /linux-6.15/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c-pxa-pci-ce4100.txt | 21 offset from be base of the BAR (which would be 23 the same BAR)
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| /linux-6.15/Documentation/translations/zh_CN/userspace-api/accelerators/ |
| H A D | ocxl.rst | 68 设备被扫描并且BAR(基址寄存器)被分配。像“lspci”的命令因此可以被用于查看
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| /linux-6.15/Documentation/driver-api/pci/ |
| H A D | p2pdma.rst | 60 functionality. For example, if a specific RNIC added a BAR with some 69 A provider simply needs to register a BAR (or a portion of a BAR)
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| /linux-6.15/drivers/firmware/broadcom/ |
| H A D | Kconfig | 21 a PCI BAR.
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| /linux-6.15/Documentation/driver-api/driver-model/ |
| H A D | devres.rst | 395 pcim_iomap() : do iomap() on a single BAR 397 pcim_iomap_table() : array of mapped addresses indexed by BAR 398 pcim_iounmap() : do iounmap() on a single BAR
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| /linux-6.15/Documentation/accel/qaic/ |
| H A D | aic100.rst | 46 * The first BAR is 4K in size, and exposes the MHI interface to the host. 48 * The second BAR is 2M in size, and exposes the DMA Bridge interface to the 51 * The third BAR is variable in size based on an individual AIC100's 52 configuration, but defaults to 64K. This BAR currently has no purpose. 265 DBC registers are exposed to the host via the second BAR. Each DBC consumes 266 4KB of space in the BAR.
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| /linux-6.15/Documentation/driver-api/ |
| H A D | men-chameleon-bus.rst | 67 header lists the device id, PCI BAR, offset from the beginning of the PCI 68 BAR, size in the FPGA, interrupt number and some other properties currently
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| H A D | switchtec.rst | 97 NT EP BAR 2 will be dynamically configured as a Direct Window, and
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| /linux-6.15/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| H A D | switchdev.rst | 79 A subfunction has a dedicated window in PCI BAR space that is not shared 82 PCI BAR space.
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| /linux-6.15/Documentation/ABI/testing/ |
| H A D | sysfs-bus-pci | 486 These files provide an interface to PCIe Resizable BAR support. 487 A file is created for each BAR resource (N) supported by the 488 PCIe Resizable BAR extended capability of the device. Reading 494 The bitmap represents supported resource sizes for the BAR, 496 example the device supports 64MB, 128MB, and 256MB BAR sizes.
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| /linux-6.15/Documentation/devicetree/bindings/net/dsa/ |
| H A D | mscc,ocelot.yaml | 45 EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
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