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Searched refs:AMDGPU_VCN_STACK_SIZE (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c349 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v5_0_1_mc_resume()
353 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_1_mc_resume()
355 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_1_mc_resume()
449 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
455 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
459 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
H A Dvcn_v5_0_0.c409 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v5_0_0_mc_resume()
413 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_0_mc_resume()
415 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v5_0_0_mc_resume()
507 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
512 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
515 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0_3.c483 AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_mc_resume()
488 AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_3_mc_resume()
491 AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_3_mc_resume()
589 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
595 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
599 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1059 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_start_sriov()
1062 AMDGPU_VCN_STACK_SIZE; in vcn_v4_0_3_start_sriov()
H A Dvcn_v2_0.c411 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_mc_resume()
415 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
417 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
499 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
504 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
507 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1990 AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_start_sriov()
1996 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_start_sriov()
2001 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c643 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
647 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
649 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
730 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
735 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
738 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1480 AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_sriov_start()
1485 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_sriov_start()
1490 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_sriov_start()
H A Dvcn_v4_0_5.c431 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_5_mc_resume()
435 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_5_mc_resume()
437 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_5_mc_resume()
532 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
537 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v4_0_5_mc_resume_dpg_mode()
541 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v4_0.c492 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_mc_resume()
496 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
498 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
589 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
594 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
597 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1427 AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_start_sriov()
1430 AMDGPU_VCN_STACK_SIZE; in vcn_v4_0_start_sriov()
H A Dvcn_v3_0.c549 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_mc_resume()
553 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
555 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
636 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
641 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
644 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1458 AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_start_sriov()
1461 AMDGPU_VCN_STACK_SIZE; in vcn_v3_0_start_sriov()
H A Dvcn_v1_0.c380 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v1_0_mc_resume_spg_mode()
384 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
386 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
452 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
457 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
460 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
H A Damdgpu_vcn.h29 #define AMDGPU_VCN_STACK_SIZE (128*1024) macro
H A Damdgpu_vcn.c198 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; in amdgpu_vcn_sw_init()