Home
last modified time | relevance | path

Searched refs:AMDGPU_VCN_CONTEXT_SIZE (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.h30 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) macro
H A Dvcn_v5_0_1.c357 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_1_mc_resume()
463 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
H A Dvcn_v4_0_3.c494 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_mc_resume()
603 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1074 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_start_sriov()
H A Dvcn_v5_0_0.c417 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_0_mc_resume()
519 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v2_0.c419 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_mc_resume()
511 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
2007 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_start_sriov()
H A Dvcn_v4_0.c500 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_mc_resume()
601 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1442 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_start_sriov()
H A Dvcn_v3_0.c557 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_mc_resume()
648 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1473 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_start_sriov()
H A Dvcn_v2_5.c651 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
742 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1496 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_sriov_start()
H A Dvcn_v4_0_5.c439 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_5_mc_resume()
546 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v1_0.c388 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v1_0_mc_resume_spg_mode()
463 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
H A Damdgpu_vcn.c198 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; in amdgpu_vcn_sw_init()