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Searched refs:AMDGPU_IRQ_STATE_DISABLE (Results 1 – 25 of 32) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_irq.h42 AMDGPU_IRQ_STATE_DISABLE, enumerator
H A Damdgpu_irq.c143 AMDGPU_IRQ_STATE_DISABLE); in amdgpu_irq_disable_all()
540 state = AMDGPU_IRQ_STATE_DISABLE; in amdgpu_irq_update()
H A Dsi_dma.c585 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()
601 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()
H A Dsdma_v2_4.c994 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()
1010 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()
H A Damdgpu_vkms.c189 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; in amdgpu_vkms_crtc_init()
H A Dcik_sdma.c1105 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()
1121 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()
H A Dsdma_v3_0.c1332 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()
1348 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()
H A Ddce_v8_0.c2958 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()
3009 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vline_interrupt_state()
3037 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_hpd_interrupt_state()
3152 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v8_0_set_pageflip_interrupt_state()
H A Dgmc_v12_0.c58 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v12_0_vm_fault_interrupt_state()
H A Dgmc_v11_0.c67 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v11_0_vm_fault_interrupt_state()
H A Dgfx_v6_0.c3210 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3231 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3273 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_reg_fault_state()
3298 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_inst_fault_state()
H A Ddce_v10_0.c3024 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()
3053 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vline_interrupt_state()
3083 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_hpd_irq_state()
3161 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v10_0_set_pageflip_irq_state()
H A Dgmc_v10_0.c68 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v10_0_vm_fault_interrupt_state()
H A Dgmc_v6_0.c1046 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v6_0_vm_fault_interrupt_state()
H A Ddce_v11_0.c3155 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()
3184 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vline_interrupt_state()
3214 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_hpd_irq_state()
3292 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v11_0_set_pageflip_irq_state()
H A Dgmc_v9_0.c435 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_ecc_interrupt_state()
487 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_vm_fault_interrupt_state()
H A Dgfx_v7_0.c4630 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()
4681 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_compute_eop_interrupt_state()
4704 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_reg_fault_state()
4729 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_inst_fault_state()
H A Dgfx_v8_0.c6412 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_gfx_eop_interrupt_state()
6451 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_compute_eop_interrupt_state()
6472 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_reg_fault_state()
6483 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_inst_fault_state()
6535 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_cp_ecc_int_state()
6580 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_sq_int_state()
H A Dgfx_v12_0.c4646 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v12_0_set_gfx_eop_interrupt_state()
4697 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v12_0_set_compute_eop_interrupt_state()
4812 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v12_0_set_priv_reg_fault_state()
4858 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v12_0_set_bad_op_fault_state()
4903 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v12_0_set_priv_inst_fault_state()
H A Dgfx_v9_4_3.c3053 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3105 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_4_3_set_priv_reg_fault_state()
3145 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_4_3_set_bad_op_fault_state()
3184 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_4_3_set_priv_inst_fault_state()
H A Ddce_v6_0.c2987 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_crtc_vblank_interrupt_state()
3022 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_hpd_interrupt_state()
3137 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v6_0_set_pageflip_interrupt_state()
H A Dgfx_v11_0.c6187 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()
6244 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_compute_eop_interrupt_state()
6359 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_priv_reg_fault_state()
6405 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_bad_op_fault_state()
6450 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_priv_inst_fault_state()
6559 if (state == AMDGPU_IRQ_STATE_DISABLE) {
H A Dgfx_v9_0.c5957 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
6004 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
6055 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_reg_fault_state()
6091 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_bad_op_fault_state()
6124 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_inst_fault_state()
6151 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_cp_ecc_error_state()
H A Dgmc_v7_0.c1236 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v7_0_vm_fault_interrupt_state()
H A Dgmc_v8_0.c1398 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v8_0_vm_fault_interrupt_state()

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