Home
last modified time | relevance | path

Searched refs:A8 (Results 1 – 25 of 53) sorted by relevance

123

/linux-6.15/Documentation/devicetree/bindings/arm/
H A Darm,realview.yaml14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
38 - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
40 Cortex CPU family, including a Cortex-A8 test chip.
H A Dapple.yaml22 Devices based on the "A8" SoC:
155 - description: Apple A8 SoC based platforms
/linux-6.15/Documentation/admin-guide/device-mapper/
H A Ddm-raid.rst129 A4 A4 A5 A6 A6 A7 A7 A8 A8
145 A3 A4 A4 A5 A6 A5 A6 A7 A8
146 A5 A6 A7 A8 A9 A9 A10 A11 A12
149 A4 A3 A6 A4 A5 A6 A5 A8 A7
150 A6 A5 A9 A7 A8 A10 A9 A12 A11
162 A3 A4 A4 A5 A6 A5 A6 A7 A8
163 A4 A3 A6 A4 A5 A6 A5 A8 A7
164 A5 A6 A7 A8 A9 A9 A10 A11 A12
165 A6 A5 A9 A7 A8 A10 A9 A12 A11
/linux-6.15/arch/arm64/boot/dts/exynos/
H A Dexynos7885-jackpotlte.dts3 * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
16 model = "Samsung Galaxy A8 (2018)";
/linux-6.15/arch/arm64/boot/dts/apple/
H A Dt7000-common.dtsi5 * This file contains parts common to all Apple A8 devices.
H A Dt7000.dtsi3 * Apple T7000 "A8" SoC
192 /* Note that A8 doesn't actually have a hypervisor (EL2 is not implemented). */
H A Dt7000-pmgr.dtsi3 * PMGR Power domains for the Apple T7000 "A8" SoC
/linux-6.15/Documentation/devicetree/bindings/display/panel/
H A Danbernic,rg35xx-plus-panel.yaml7 title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel
/linux-6.15/arch/arm/mach-versatile/
H A DKconfig215 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
219 Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2400-pinctrl.yaml219 pins = "A8";
/linux-6.15/arch/arm/boot/dts/arm/
H A Darm-realview-pba8.dts27 model = "ARM RealView Platform Baseboard for Cortex-A8";
/linux-6.15/Documentation/ABI/stable/
H A Dsysfs-class-tpm139 A7 1F 3C A8 D0 12 15 3E CA 0E BD FA 24 CD 33 C6
144 F7 02 71 CF 15 AE 16 DD D1 C1 8E A8 CF 9B 50 7B
/linux-6.15/Documentation/arch/arm/
H A Dsunxi.rst20 * ARM Cortex-A8 based SoCs
/linux-6.15/arch/arm/crypto/
H A Dsha1-armv4-large.S50 @ issue Cortex A8 core was measured to process input block in
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
62 @ improvement on Cortex A8 core and 12.2 cycles per byte.
/linux-6.15/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g4.c471 #define A8 56 macro
474 SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S);
475 SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC);
476 PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
527 FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
1855 A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
1926 ASPEED_PINCTRL_PIN(A8),
2454 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
2455 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
H A Dpinctrl-aspeed-g5.c1859 #define A8 233 macro
1860 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
1861 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1862 PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
1864 FUNC_GROUP_DECL(USB2AH, A7, A8);
1865 FUNC_GROUP_DECL(USB2AD, A7, A8);
1921 ASPEED_PINCTRL_PIN(A8),
/linux-6.15/Documentation/hwmon/
H A Dk10temp.rst20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
/linux-6.15/Documentation/devicetree/bindings/arm/samsung/
H A Dsamsung-boards.yaml218 - samsung,jackpotlte # Samsung Galaxy A8 (2018)
/linux-6.15/Documentation/admin-guide/media/
H A Dvisl.rst163 00000040: e8c3 4320 b4ba a226 cbc1 4138 3a12 32d6 ..C ...&..A8:.2.
/linux-6.15/arch/arm/mm/
H A Dproc-v7.S501 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
591 @ Cortex-A8 - always needs bpiall switch_mm implementation
/linux-6.15/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-zaius.dts470 pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
/linux-6.15/arch/arm64/boot/dts/ti/
H A Dk3-j7200-som-p0.dtsi121 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
/linux-6.15/arch/arm64/boot/dts/amlogic/
H A Dmeson-libretech-cottonwood.dtsi261 * DO: 13/A8
/linux-6.15/arch/arm/boot/dts/st/
H A Dste-dbx5x0-pinctrl.dtsi457 /* MC2 without feedback clock on A8 */
/linux-6.15/arch/arm/
H A DKconfig563 This option enables the workaround for the 430973 Cortex-A8
567 to physical address re-mapping, Cortex-A8 does not recover from the
568 stale interworking branch prediction. This results in Cortex-A8
580 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
596 This option enables the workaround for the 460075 Cortex-A8 (r2p0)

123