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/linux-6.15/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
349 /* A7 CPU core voltage */
352 regulator-name = "A7 Vcore";
356 label = "A7 Vcore";
367 /* Total current for the three A7 cores */
370 label = "A7 Icore";
388 /* Total power for the three A7 cores */
391 label = "A7 Pcore";
402 /* Total energy for the three A7 cores */
[all …]
/linux-6.15/Documentation/arch/arm/
H A Dsunxi.rst47 * Single ARM Cortex-A7 based SoCs
54 * Dual ARM Cortex-A7 based SoCs
71 * Quad ARM Cortex-A7 based SoCs
123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
130 * Octa ARM Cortex-A7 based SoCs
/linux-6.15/arch/arm/include/debug/
H A Dexynos.S27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
/linux-6.15/Documentation/arch/arm/stm32/
H A Dstm32mp151-overview.rst11 - Single Cortex-A7 application core
18 - Cortex-A7 core running up to @800MHz
H A Dstm32mp13-overview.rst11 - One Cortex-A7 application core
18 - Cortex-A7 core running up to @900MHz
H A Dstm32mp157-overview.rst11 - Dual core Cortex-A7 application core
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dqcom,a7pll.yaml7 title: Qualcomm A7 PLL clock
13 The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
H A Dimx7ulp-scg-clock.yaml18 and A7 domain. Except for a few clock sources shared between two
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26 Note: this binding doc is only for A7 clock domain.
H A Dimx7ulp-pcc-clock.yaml18 and A7 domain. Except for a few clock sources shared between two
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26 Note: this binding doc is only for A7 clock domain.
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx7ulp-pinctrl.txt3 i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
7 This binding doc is only for the IOMUXC1 support in A7 Domain and it only
/linux-6.15/arch/arm64/boot/dts/rockchip/
H A Drk3566-radxa-zero-3.dtsi110 /* GPIO0_A0 - A7 */
123 /* GPIO1_A0 - A7 */
137 /* GPIO2_A0 - A7 */
149 /* GPIO3_A0 - A7 */
167 /* GPIO4_A0 - A7 */
H A Drk3308-rock-pi-s.dts171 /* GPIO0_A0 - A7 */
187 /* GPIO1_A0 - A7 */
201 /* GPIO2_A0 - A7 */
219 /* GPIO3_A0 - A7 */
H A Drk3328-rock-pi-e.dts184 /* GPIO0_A0 - A7 */
196 /* GPIO1_A0 - A7 */
208 /* GPIO2_A0 - A7 */
224 /* GPIO3_A0 - A7 */
/linux-6.15/Documentation/admin-guide/device-mapper/
H A Ddm-raid.rst129 A4 A4 A5 A6 A6 A7 A7 A8 A8
145 A3 A4 A4 A5 A6 A5 A6 A7 A8
146 A5 A6 A7 A8 A9 A9 A10 A11 A12
149 A4 A3 A6 A4 A5 A6 A5 A8 A7
150 A6 A5 A9 A7 A8 A10 A9 A12 A11
162 A3 A4 A4 A5 A6 A5 A6 A7 A8
163 A4 A3 A6 A4 A5 A6 A5 A8 A7
164 A5 A6 A7 A8 A9 A9 A10 A11 A12
165 A6 A5 A9 A7 A8 A10 A9 A12 A11
/linux-6.15/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-qcom-dc-scm-v1.dts95 /*A0-A7*/ "","","","","","","","",
130 /*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
H A Daspeed-bmc-vegman-n110.dts15 …/*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","…
52 …/*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_AB…
/linux-6.15/arch/arm/mach-exynos/
H A DKconfig51 Samsung Exynos3 (Cortex-A7) SoC based systems
67 Samsung Exynos5 (Cortex-A15/A7) SoC based systems
/linux-6.15/arch/arm/boot/dts/rockchip/
H A Drk3128-xpi-3128.dts282 gpio-line-names = /* GPIO0 A0-A7 */
297 gpio-line-names = /* GPIO1 A0-A7 */
312 gpio-line-names = /* GPIO2 A0-A7 */
327 gpio-line-names = /* GPIO3 A0-A7 */
/linux-6.15/arch/arm/mach-bcm/
H A DKconfig174 BCM53573 series is set of SoCs using ARM Cortex-A7 CPUs with wireless
220 bool "Cortex-A7 SoCs"
222 Say Y if you intend to run the kernel on a Broadcom Broadband ARM A7
225 This enables support for Broadcom BCA ARM A7 broadband chipsets,
/linux-6.15/arch/arm64/boot/dts/apple/
H A Ds5l8960x-mini3.dtsi4 * Based on A7 (APL0698), up to 1.3GHz
H A Ds5l8960x.dtsi3 * Apple S5L8960X "A7" SoC
137 /* Note that A7 doesn't actually have a hypervisor (EL2 is not implemented). */
H A Ds5l8965x-opp.dtsi3 * Operating points for Apple S5L8965X "A7" Rev A SoC, Up to 1392 MHz
H A Ds5l8960x-opp.dtsi3 * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz
/linux-6.15/arch/arm/mach-mstar/
H A DKconfig12 based on Armv7 cores like the Cortex A7 and share the same
/linux-6.15/Documentation/devicetree/bindings/arm/
H A Dsunplus,sp7021.yaml14 ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.

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