| /freebsd-14.2/contrib/llvm-project/compiler-rt/lib/builtins/arm/ |
| H A D | subsf3vfp.S | 22 vsub.f32 s0, s0, s1 26 vsub.f32 s14, s14, s15
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| H A D | subdf3vfp.S | 21 vsub.f64 d0, d0, d1 25 vsub.f64 d6, d6, d7
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| /freebsd-14.2/sys/arm/nvidia/drm2/ |
| H A D | tegra_fb.c | 271 int hsub, vsub, i; in tegra_drm_fb_create() local 279 vsub = drm_format_vert_chroma_subsampling(cmd->pixel_format); in tegra_drm_fb_create() 287 height /= vsub; in tegra_drm_fb_create()
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| /freebsd-14.2/lib/libc/arm/aeabi/ |
| H A D | aeabi_vfp_float.S | 184 vsub.f32 s0, s0, s1
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| H A D | aeabi_vfp_double.S | 197 vsub.f64 d0, d0, d1
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| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_fp16.td | 118 def VSUBHS : SInst<"vsub", "111", "Sh">;
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| H A D | arm_neon.td | 338 def VSUB : IOpInst<"vsub", "...", 764 def SUB : IOpInst<"vsub", "...", "dQd", OP_SUB>; 1306 def SCALAR_SUB : SInst<"vsub", "111", "SlSUl">; 1702 def VSUBH : SOpInst<"vsub", "...", "hQh", OP_SUB>;
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| H A D | riscv_vector.td | 1170 defm vsub : RVVIntBinBuiltinSet;
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| /freebsd-14.2/sys/dev/drm2/ |
| H A D | drm_crtc.c | 2247 int ret, hsub, vsub, num_planes, i; in framebuffer_check() local 2256 vsub = drm_format_vert_chroma_subsampling(r->pixel_format); in framebuffer_check() 2264 if (r->height == 0 || r->height % vsub) { in framebuffer_check() 2271 unsigned int height = r->height / (i != 0 ? vsub : 1); in framebuffer_check()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 38894 "$Vd32.hf = vsub($Vu32.hf,$Vv32.hf)", 38998 "$Vd32.sf = vsub($Vu32.sf,$Vv32.sf)", 39011 "$Vd32.b = vsub($Vu32.b,$Vv32.b)", 39038 "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", 39206 "$Vd32.h = vsub($Vu32.h,$Vv32.h)", 39233 "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", 39370 "$Vdd32.w = vsub($Vu32.h,$Vv32.h)", 39395 "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", 39539 "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", 39616 "$Vd32.w = vsub($Vu32.w,$Vv32.w)", [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 431 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 438 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 449 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
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| H A D | ARMInstrMVE.td | 2058 : MVE_VADDSUB_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>; 3783 : MVE_VADDSUB_fp_m<"vsub", 1, VTI, fsub, int_arm_mve_sub_predicated, IdentityVec>; 5271 : MVE_VADDSUB_qr_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>; 5422 defm MVE_VSUB_qr_f32 : MVE_VADDSUB_qr_f<"vsub", MVE_v4f32, 0b1, fsub, 5424 defm MVE_VSUB_qr_f16 : MVE_VADDSUB_qr_f<"vsub", MVE_v8f16, 0b1, fsub,
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| H A D | ARMInstrNEON.td | 5068 "vsub", "i", sub, 0>; 5069 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32", 5071 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", 5073 def VSUBhd : N3VD<0, 0, 0b11, 0b1101, 0, IIC_VBIND, "vsub", "f16", 5076 def VSUBhq : N3VQ<0, 0, 0b11, 0b1101, 0, IIC_VBINQ, "vsub", "f16", 9125 def : NEONMnemonicAlias<"vsubq", "vsub">;
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsRISCV.td | 1377 defm vsub : RISCVBinaryAAX;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoV.td | 1103 defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
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| H A D | RISCVInstrInfoVPseudos.td | 6221 // Match vrsub with 2 vector operands to vsub.vv by swapping operands. This
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX512.td | 5477 defm VSUB : avx512_binop_s_round<0x5C, "vsub", any_fsub, X86fsubs, X86fsubRnds, 5682 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", any_fsub, fsub, HasAVX512, 5684 avx512_fp_binop_ph<0x5C, "vsub", any_fsub, fsub, SchedWriteFAddSizes>, 5685 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SchedWriteFAddSizes>;
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