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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td75 TILE:$src4), []>;
120 let isPseudo = true, Constraints = "$src4 = $dst" in {
122 GR16:$src2, GR16:$src3, TILE:$src4,
128 GR16:$src2, GR16:$src3, TILE:$src4,
134 GR16:$src2, GR16:$src3, TILE:$src4,
140 GR16:$src2, GR16:$src3, TILE:$src4,
179 let isPseudo = true, Constraints = "$src4 = $dst" in
181 GR16:$src2, GR16:$src3, TILE:$src4,
210 let isPseudo = true, Constraints = "$src4 = $dst" in {
212 GR16:$src2, GR16:$src3, TILE:$src4,
[all …]
H A DX86InstrXOP.td421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
423 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
430 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
433 (i8 timm:$src4))))]>, REX_W,
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
438 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
441 RC:$src3, (i8 timm:$src4))))]>,
450 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
[all …]
H A DX86InstrAVX512.td11632 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11640 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11681 _.RC:$src2, (i8 timm:$src4)),
11690 _.RC:$src2, (i8 timm:$src4)),
11708 _.RC:$src1, (i8 timm:$src4)),
11727 (VPTERNLOG321_imm8 timm:$src4))>;
11735 (VPTERNLOG132_imm8 timm:$src4))>;
11898 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
11905 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
11947 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td114 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
115 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
117 HvxVR:$src3, imm:$src4),
118 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
122 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
123 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
125 HvxVR:$src3, imm:$src4),
126 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
H A DHexagonIntrinsicsV60.td271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 IntRegs:$src3, imm:$src4),
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 HvxVR:$src3, IntRegs:$src4),
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
293 HvxVR:$src3, IntRegs:$src4),
[all …]
H A DHexagonDepMapAsm2Intrin.td612 def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4),
2417 def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
2425 def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
3307 def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3309 def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3311 def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3319 def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
3323 def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
3331 def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3333 def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
[all …]
H A DHexagonIntrinsicsV5.td184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
147 (XformImm u5_0ImmPred:$src4))>;
/freebsd-14.2/sys/net/
H A Dif_stf.c500 struct sockaddr_in dst4, src4; in stf_output() local
594 src4.sin_addr.s_addr = sc->srcv4_addr; in stf_output()
595 else if (stf_getin4addr(sc, &src4, addr6, mask6) == NULL) { in stf_output()
601 bcopy(&src4.sin_addr, &ip->ip_src, sizeof(ip->ip_src)); in stf_output()
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dr8a7745-iwg22d-sodimm.dts295 capture = <&ssi4>, <&src4>, <&dvc1>;
H A Dr8a7778.dtsi283 src4: src-4 { }; label
662 "sru-src3", "sru-src4", "sru-src5",
H A Dr8a7742-iwg21d-q7.dts392 playback = <&ssi4>, <&src4>, <&dvc1>;
H A Dr8a7793.dtsi1074 src4: src-4 { label
H A Dr8a7794.dtsi1056 src4: src-4 { label
H A Dr8a7745.dtsi1220 src4: src-4 { label
H A Dr8a7743.dtsi1290 src4: src-4 { label
H A Dr8a7744.dtsi1290 src4: src-4 { label
H A Dr8a7742.dtsi1261 src4: src-4 { label
/freebsd-14.2/sys/ofed/drivers/infiniband/core/
H A Dib_cma.c3530 struct sockaddr_in *src4, *dst4; in sdp_format_hdr() local
3532 src4 = (struct sockaddr_in *) cma_src_addr(id_priv); in sdp_format_hdr()
3536 sdp_hdr->src_addr.ip4.addr = src4->sin_addr.s_addr; in sdp_format_hdr()
3538 sdp_hdr->port = src4->sin_port; in sdp_format_hdr()
3566 struct sockaddr_in *src4, *dst4; in cma_format_hdr() local
3568 src4 = (struct sockaddr_in *) cma_src_addr(id_priv); in cma_format_hdr()
3572 cma_hdr->src_addr.ip4.addr = src4->sin_addr.s_addr; in cma_format_hdr()
3574 cma_hdr->port = src4->sin_port; in cma_format_hdr()
/freebsd-14.2/sys/contrib/device-tree/Bindings/sound/
H A Drenesas,rsnd.txt51 &src4 &ssi4
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td3077 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
3081 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
3084 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
3088 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
3091 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
3095 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
3098 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
3102 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
3105 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
3109 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
520 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1290 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1332 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
2067 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2068 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2087 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2088 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2385 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2425 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
[all …]
/freebsd-14.2/sys/netinet/
H A Dsctp_output.c5339 struct sockaddr_in *src4; in sctp_are_there_new_addresses() local
5342 src4 = (struct sockaddr_in *)src; in sctp_are_there_new_addresses()
5343 if (sa4->sin_addr.s_addr == src4->sin_addr.s_addr) { in sctp_are_there_new_addresses()
5518 struct sockaddr_in *src4 = (struct sockaddr_in *)src; in sctp_send_initiate_ack() local
5659 stc.address[0] = src4->sin_addr.s_addr; in sctp_send_initiate_ack()
5672 if ((IN4_ISPRIVATE_ADDRESS(&src4->sin_addr)) || in sctp_send_initiate_ack()
/freebsd-14.2/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a774c0.dtsi1426 src4: src-4 { label

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