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/freebsd-14.2/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h154 __builtin_ia32_tdpbssd((dst), (src0), (src1))
173 __builtin_ia32_tdpbsud((dst), (src0), (src1))
192 __builtin_ia32_tdpbusd((dst), (src0), (src1))
211 __builtin_ia32_tdpbuud((dst), (src0), (src1))
229 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
371 dst->tile = _tile_dpbssd_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbssd()
394 dst->tile = _tile_dpbsud_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbsud()
417 dst->tile = _tile_dpbusd_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbusd()
440 dst->tile = _tile_dpbuud_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbuud()
492 dst->tile = _tile_dpbf16ps_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbf16ps()
[all …]
H A Damxcomplexintrin.h139 static void __tile_cmmimfp16ps(__tile1024i *dst, __tile1024i src0, in __tile_cmmimfp16ps() argument
141 dst->tile = _tile_cmmimfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmimfp16ps()
142 dst->tile, src0.tile, src1.tile); in __tile_cmmimfp16ps()
162 static void __tile_cmmrlfp16ps(__tile1024i *dst, __tile1024i src0, in __tile_cmmrlfp16ps() argument
164 dst->tile = _tile_cmmrlfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmrlfp16ps()
165 dst->tile, src0.tile, src1.tile); in __tile_cmmrlfp16ps()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td208 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
211 // out = (src1 > src0) ? 1 : 0
272 // src0: vec4(src, 0, 0, mask)
349 // i32 or f32 src0
421 [(int_amdgcn_class node:$src0, node:$src1),
445 [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
469 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
470 (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
473 [(int_amdgcn_mul_i24 node:$src0, node:$src1),
474 (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
[all …]
H A DAMDGPUInstructions.td192 (ops node:$src0),
193 (op $src0),
203 (op $src0, $src1),
286 def csh_mask_16 : PatFrag<(ops node:$src0), (and node:$src0, imm),
291 def csh_mask_32 : PatFrag<(ops node:$src0), (and node:$src0, imm),
296 def csh_mask_64 : PatFrag<(ops node:$src0), (and node:$src0, imm),
327 (ops node:$src0), (srl_oneuse node:$src0, (i32 16))
332 (ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
789 (dt rc:$src0)
802 (BIT_ALIGN $src0, $src0, $src1)
[all …]
H A DSIInstructions.td71 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
82 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
239 (ins VGPR_32:$src0),
243 (ins VGPR_32:$src0),
2634 (S_NOT_B64 $src0)
2639 (S_NOT_B64 $src0)
2673 (S_NOT_B32 $src0)
2678 (S_NOT_B32 $src0)
3160 (COPY $src0)
3297 (COPY $src0)
[all …]
H A DSOPInstructions.td66 bits<8> src0;
145 opName, (outs), (ins SReg_64:$src0), "$src0", pattern> {
152 (Op $src0),
467 (ins SplitBarrier:$src0), "$src0", []>{
486 (ins SplitBarrier:$src0), "$src0", [(int_amdgcn_s_barrier_signal timm:$src0)]>{
492 (ins SplitBarrier:$src0), "$src0", [(set SCC, (int_amdgcn_s_barrier_signal_isfirst timm:$src0))]>{
499 (ins SplitBarrier:$src0), "$src0", []>{
505 (ins SplitBarrier:$src0), "$src0", []>{
512 (ins SplitBarrier:$src0), "$sdst, $src0", []>{
571 bits<8> src0;
[all …]
H A DEvergreenInstructions.td464 (fcopysign f32:$src0, f32:$src1),
469 (fcopysign f32:$src0, f64:$src1),
475 (fcopysign f64:$src0, f64:$src1),
477 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
484 (fcopysign f64:$src0, f32:$src1),
486 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
505 (fshr i32:$src0, i32:$src1, i32:$src2),
506 (BIT_ALIGN_INT_eg $src0, $src1, $src2)
560 let src0 = 0;
773 def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
[all …]
H A DVOPInstructions.td236 bits<9> src0;
358 bits<9> src0;
381 bits<9> src0;
417 bits<10> src0;
445 bits<10> src0;
515 bits<8> src0;
551 bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
705 bits<8> src0;
733 bits<8> src0;
1080 (Op $src0),
[all …]
H A DR600Instructions.td435 (ins i32imm:$src0),
436 "INTERP_LOAD $src0 : $dst">;
683 (ins rc:$src0),
684 "FABS $dst, $src0",
690 (ins rc:$src0),
691 "FNEG $dst, $src0",
1079 (ins R600_Reg128:$src0),
1080 "CUBE $dst $src0",
1217 (fdiv f32:$src0, f32:$src1),
1718 (cnd $src0, $src1, $src2)
[all …]
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
38 : EXPCommon<0, done, "exp$tgt $src0, $src1, $src2, $src3"
46 : EXPCommon<row, done, name#"$tgt $src0, $src1, $src2, $src3"
149 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
152 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
158 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
161 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
167 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
169 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
H A DVOP3Instructions.td71 let Ins64 = (ins InterpSlot:$src0,
181 // result = src0 * src1 + src2
188 // result = src0 * src1 + src2
428 (op i16:$src0, i16:$src1, i16:$src2),
440 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
503 (ops node:$src0, node:$src1), (shl node:$src0, node:$src1),
603 // to the new src0.
697 (V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
734 (EXTRACT_SUBREG (inst $src0, $src1,
755 (inst $src0, $src1, $src2, 0 /* clamp */)
[all …]
H A DVOP2Instructions.td15 bits<9> src0;
27 bits<9> src0;
819 (Inst $src0, $src1),
820 (Inst $src1, $src0)
828 (Inst $src0, $src1, 0),
829 (Inst $src1, $src0, 0)
932 (inst $src0_modifiers, $src0,
1147 (and vt:$src0, vt:$src1),
1152 (or vt:$src0, vt:$src1),
1157 (xor vt:$src0, vt:$src1),
[all …]
H A DVINTERPInstructions.td16 bits<9> src0;
34 let Inst{40-32} = src0;
77 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
95 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
130 (VINTERPMods f32:$src0, i32:$src0_modifiers),
133 (inst $src0_modifiers, $src0,
149 (pat[0] f32:$src0, i32:$src0_modifiers),
153 (inst $src0_modifiers, $src0,
H A DAMDGPUGISel.td308 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
309 (inst src0_vt:$src0, src1_vt:$src1)
318 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
319 (inst src0_vt:$src0, src1_vt:$src1)
328 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
329 (inst src0_vt:$src0, src1_vt:$src1)
338 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
339 (inst src0_vt:$src0, src1_vt:$src1)
348 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
349 (inst src0_vt:$src1, src1_vt:$src0)
[all …]
H A DVOP3PInstructions.td173 (mixlo_inst $src0_modifiers, $src0,
187 (v2f16 (mixhi_inst $src0_modifiers, $src0,
200 (v2f16 (mixhi_inst $src0_modifiers, $src0,
229 (mixlo_inst $src0_modifiers, $src0,
239 (v2f16 (mixhi_inst $src0_modifiers, $src0,
319 (ops node:$src0, node:$src1),
346 (ops node:$src0, node:$src1),
431 def : GCNPat < (int_amdgcn_sdot8 i32:$src0,
434 (V_DOT8_I32_IU4 (i32 9), i32:$src0,
438 def : GCNPat < (int_amdgcn_sdot4 i32:$src0,
[all …]
H A DSIInstrInfo.td661 (srl $src0, $src1)
666 (sra $src0, $src1)
671 (shl $src0, $src1)
676 (add (ctpop $src0), $src1)
681 (not (xor $src0, $src1))
1704 (ins Src0RC:$src0))
1954 string src0 = ", $src0";
1965 string src0 = ", $src0" # XorY;
1977 string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
2000 string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
[all …]
H A DVOP1Instructions.td15 bits<9> src0;
17 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);
176 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
242 (ins VRegOrLdsSrc_32:$src0),
243 "v_readfirstlane_b32 $vdst, $src0",
261 bits<9> src0;
263 let Inst{8-0} = src0;
375 // Restrict src0 to be VGPR
544 let Asm32 = " $vdst, $src0";
723 let Asm32 = " $vdst, $src0";
[all …]
H A DSIPeepholeSDWA.cpp309 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
344 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
539 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
580 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
649 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
666 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
722 MachineOperand *OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
728 OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
903 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0)) in pseudoOpConvertToVOP2()
1015 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
[all …]
H A DCaymanInstructions.td23 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
26 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
61 (AMDGPUurecip i32:$src0),
62 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrCompiler.td19 def shiftMask_64 : PatFrag<(ops node:$src0), (and node:$src0, imm), [{
25 def mshl_#width : PatFrags<(ops node:$src0, node:$src1),
26 [(shl node:$src0, node:$src1), (shl node:$src0, (shiftMask node:$src1))]>;
28 def msrl_#width : PatFrags<(ops node:$src0, node:$src1),
29 [(srl node:$src0, node:$src1), (srl node:$src0, (shiftMask node:$src1))]>;
31 def msra_#width : PatFrags<(ops node:$src0, node:$src1),
32 [(sra node:$src0, node:$src1), (sra node:$src0, (shiftMask node:$src1))]>;
/freebsd-14.2/lib/libc/string/
H A Dbcopy.c59 (void *dst0, const void *src0, size_t length) in memcpy() argument
64 bcopy(const void *src0, void *dst0, size_t length) in memcpy()
68 const char *src = src0; in memcpy()
/freebsd-14.2/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl3060 my ($a,$b,$src0) = @_;
3063 " mov $b, $src0
3073 my ($a,$src0) = @_;
3076 " mov 8*0+$a, $src0
3227 $src0 = "%rax";
3245 $src0 = "%rdx";
3423 mov $M(%rsp), $src0
3478 $src0 = "%rax";
3496 $src0 = "%rdx";
3858 $src0 = "%rax";
[all …]
/freebsd-14.2/sys/libkern/
H A Dbcopy.c69 memcpy(void *dst0, const void *src0, size_t length) in memcpy() argument
76 src = src0; in memcpy()
/freebsd-14.2/sys/cddl/dev/kinst/
H A Dkinst.c81 volatile const unsigned char *src0; in kinst_memcpy() local
84 src0 = src; in kinst_memcpy()
88 *dst0++ = *src0++; in kinst_memcpy()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td615 (ins s0_regclass:$src0, s1_regclass:$src1),
652 F_MATH_2<"min.xorsign.abs.f32 \t$dst, $src0, $src1;",
656 F_MATH_2<"min.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
660 F_MATH_2<"min.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
679 F_MATH_2<"max.xorsign.abs.f32 \t$dst, $src0, $src1;",
683 F_MATH_2<"max.ftz.xorsign.abs.f32 \t$dst, $src0, $src1;",
687 F_MATH_2<"max.NaN.xorsign.abs.f32 \t$dst, $src0, $src1;",
1082 def INT_NVVM_RCP_RN_F : F_MATH_1<"rcp.rn.f32 \t$dst, $src0;",
1086 def INT_NVVM_RCP_RZ_F : F_MATH_1<"rcp.rz.f32 \t$dst, $src0;",
1344 "mov.b64 \t{$dst, %temp}, $src0;\n\t",
[all …]

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