| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 250 MI.getOperand(0).setSubReg(KilledProdSubReg); in processBlock()
251 MI.getOperand(1).setSubReg(KilledProdSubReg); in processBlock()
252 MI.getOperand(3).setSubReg(AddSubReg); in processBlock()
266 MI.getOperand(2).setSubReg(AddSubReg); in processBlock()
271 MI.getOperand(2).setSubReg(OtherProdSubReg); in processBlock()
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| H A D | PPCVSXCopy.cpp | 134 SrcMO.setSubReg(PPC::sub_64); in processBlock()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 134 I.getOperand(1).setSubReg(DefSrcMO.getSubReg()); in processReg()
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| H A D | SIPreAllocateWWMRegs.cpp | 136 MO.setSubReg(0); in rewriteRegs()
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| H A D | GCNRewritePartialRegUses.cpp | 470 MO.setSubReg(SubReg); in rewriteReg()
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| H A D | SIFoldOperands.cpp | 879 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
1019 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
1936 MO.setSubReg(AGPRSubReg); in tryFoldPhiAGPR()
2125 MO->setSubReg(AMDGPU::NoSubRegister); in tryOptimizeAGPRPhis()
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| H A D | SIInstrInfo.cpp | 2566 UseMO->setSubReg(AMDGPU::NoSubRegister); in reMaterialize()
2572 MI->getOperand(0).setSubReg(AMDGPU::NoSubRegister); in reMaterialize()
2712 NonRegOp.setSubReg(SubReg); in swapRegAndNonRegOperand()
3428 UseMI.getOperand(0).setSubReg(0); in FoldImmediate()
3524 Src0->setSubReg(SrcSubReg); in FoldImmediate()
5839 Src0.setSubReg(Src1.getSubReg()); in legalizeOperandsVOP2()
5844 Src1.setSubReg(Src0SubReg); in legalizeOperandsVOP2()
6121 Op.setSubReg(0); in legalizeGenericOperand()
9819 Op.setSubReg(AMDGPU::sub0); in enforceOperandRCAlignment()
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| H A D | SIPeepholeSDWA.cpp | 249 To.setSubReg(From.getSubReg()); in copyRegOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 653 UseMO->setSubReg(0); in INITIALIZE_PASS_DEPENDENCY()
921 MOSrc.setSubReg(NewSubReg); in RewriteCurrentSource()
1011 MO.setSubReg(NewSubReg); in RewriteCurrentSource()
1138 MO.setSubReg(NewSubReg); in RewriteCurrentSource()
1303 NewCopy->getOperand(0).setSubReg(Def.SubReg); in rewriteSource()
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| H A D | CodeGenCommonISel.cpp | 287 UseMO.setSubReg(Op0->getSubReg()); in salvageDebugInfoForDbgValue()
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| H A D | TwoAddressInstructionPass.cpp | 1466 SrcMO.setSubReg(0); in collectTiedOperands()
1591 MO.setSubReg(0); in processTiedPairs()
1605 MO.setSubReg(0); in processTiedPairs()
1866 mi->getOperand(0).setSubReg(SubIdx); in runOnMachineFunction()
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| H A D | RegAllocFast.cpp | 974 MO.setSubReg(0); in allocVirtRegUndef()
1168 MO.setSubReg(0); in setPhysReg()
1472 MO.setSubReg(0); in allocateInstruction()
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| H A D | MachineSink.cpp | 576 MO->setSubReg(0); in PerformSinkAndFold()
1377 DbgMO.setSubReg(SrcMO->getSubReg()); in attemptDebugCopyProp()
1791 DbgOp.setSubReg(MI.getOperand(1).getSubReg()); in SalvageUnsunkDebugUsersOfCopy()
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| H A D | TargetInstrInfo.cpp | 228 CommutedMI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
232 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
233 CommutedMI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
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| H A D | MachineOperand.cpp | 90 setSubReg(SubIdx); in substVirtReg()
99 setSubReg(0); in substPhysReg()
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| H A D | VirtRegMap.cpp | 604 MO.setSubReg(0); in rewrite()
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| H A D | LiveDebugVariables.cpp | 1368 MO.setSubReg(locations[OldLocNo].getSubReg()); in splitLocation()
1553 Loc.setSubReg(0); in rewriteLocations()
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| H A D | TailDuplicator.cpp | 445 MO.setSubReg( in duplicateInstruction()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 490 void setSubReg(unsigned subReg) { in setSubReg() function
859 Op.setSubReg(SubReg);
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| H A D | MachineInstr.h | 1941 MO.setSubReg(0);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | RDFCopy.cpp | 221 Op.setSubReg(0); in run()
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| H A D | HexagonBitSimplify.cpp | 408 I->setSubReg(NewSR); in replaceRegWithSub()
427 I->setSubReg(NewSR); in replaceSubWithSub()
1966 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| H A D | HexagonExpandCondsets.cpp | 947 Op.setSubReg(RN.Sub); in renameInRange()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 512 MO.setSubReg(0); in reassign()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 327 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
815 I.getOperand(1).setSubReg(SubIdx); in selectTruncOrPtrToInt()
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