Home
last modified time | relevance | path

Searched refs:setRegClass (Results 1 – 25 of 37) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp543 MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass); in buildAtomicCompareExchangeInst()
544 MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass); in buildAtomicCompareExchangeInst()
545 MRI->setRegClass(Desired, &SPIRV::IDRegClass); in buildAtomicCompareExchangeInst()
616 MRI->setRegClass(Tmp, &SPIRV::IDRegClass); in buildAtomicCompareExchangeInst()
651 MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass); in buildAtomicRMWInst()
751 MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass); in buildBarrierInst()
955 MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass); in genWorkgroupQuery()
973 MRI->setRegClass(Extracted, &SPIRV::IDRegClass); in genWorkgroupQuery()
1262 MRI->setRegClass(Image, &SPIRV::IDRegClass); in generateReadImageInst()
1302 MRI->setRegClass(TempRegister, &SPIRV::IDRegClass); in generateReadImageInst()
[all …]
H A DSPIRVPreLegalizer.cpp90 MRI.setRegClass(Reg, RC); in addConstantsToTrack()
206 MRI.setRegClass(Reg, &SPIRV::IDRegClass); in propagateSPIRVType()
228 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
230 MRI.setRegClass(NewReg, &SPIRV::IDRegClass); in insertAssignInstr()
231 MRI.setRegClass(Reg, &SPIRV::IDRegClass); in insertAssignInstr()
365 MRI.setRegClass(IdReg, DstClass); in createNewIdReg()
416 MRI.setRegClass(DstReg, &SPIRV::IDRegClass); in processInstrsWithTypeFolding()
H A DSPIRVGlobalRegistry.cpp65 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
71 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
154 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateConstIntReg()
214 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in buildConstantInt()
257 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in buildConstantFP()
289 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass); in getOrCreateIntCompositeOrNull()
361 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass); in getOrCreateIntCompositeOrNull()
430 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateConstNullPtr()
1170 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateUndef()
H A DSPIRVCallLowering.cpp351 MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass); in lowerFormalArguments()
371 MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass); in lowerFormalArguments()
463 MRI->setRegClass(Reg, &SPIRV::IDRegClass); in lowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
79 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
141 setRegClass(Reg, NewRC); in recomputeRegClass()
H A DRegisterBankInfo.cpp148 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
H A DTailDuplicator.cpp425 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp364 Flag.setRegClass(RC->getID()); in lowerInlineAsm()
515 Flag.setRegClass(RC->getID()); in lowerInlineAsm()
H A DInstructionSelect.cpp186 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp411 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1314 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1318 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1331 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1340 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2427 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2429 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp247 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
299 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
823 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
H A DAMDGPURegisterBankInfo.cpp941 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
2570 MRI.setRegClass(DstReg, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2571 MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2572 MRI.setRegClass(SrcReg1, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2585 MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2591 MRI.setRegClass(Op1L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2601 MRI.setRegClass(Zero64, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
2603 MRI.setRegClass(CarryOut, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
H A DSIFoldOperands.cpp2024 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
2026 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
2032 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
H A DSILowerI1Copies.cpp810 MRI->setRegClass(DstReg, ST->getBoolRC()); in markAsLaneMask()
H A DAMDGPULegalizerInfo.cpp2131 MRI.setRegClass(Dst, &AMDGPU::SReg_64RegClass); in getSegmentAperture()
2791 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
2813 MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass); in buildAbsGlobalAddress()
2826 MRI.setRegClass(AddrHi, &AMDGPU::SReg_32RegClass); in buildAbsGlobalAddress()
2839 MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass); in buildAbsGlobalAddress()
6949 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
6950 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
6985 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
H A DAMDGPUInstructionSelector.cpp184 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
463 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
1042 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1573 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
2196 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2925 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h400 void setRegClass(unsigned RC) { in setRegClass() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp299 Flag.setRegClass(SP::IntPairRegClassID); in tryInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp254 Flag.setRegClass(CSKY::GPRPairRegClassID); in selectInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1332 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1334 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1336 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1334 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1356 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
2072 MRI.setRegClass(NewMI.getReg(0), &AArch64::GPR64commonRegClass); in legalizeDynStackAlloc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp507 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h702 void setRegClass(Register Reg, const TargetRegisterClass *RC);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp698 MRI.setRegClass(Reg, Info.D.RC); in setupRegisterInfo()

12