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Searched refs:setReg (Results 1 – 25 of 165) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineLoopUtils.cpp55 MO.setReg(R); in PeelSingleBlockLoop()
71 Use->setReg(R); in PeelSingleBlockLoop()
80 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
95 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
102 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
H A DTailDuplicator.cpp233 UseMO->setReg( in tailDuplicateAndUpdate()
405 MO.setReg(NewReg); in duplicateInstruction()
442 MO.setReg(VI->second.Reg); in duplicateInstruction()
457 MO.setReg(NewReg); in duplicateInstruction()
528 MI.getOperand(Idx).setReg(SrcReg); in updateSuccessorsPHIs()
539 MI.getOperand(Idx).setReg(Reg); in updateSuccessorsPHIs()
H A DBreakFalseDeps.cpp148 MO.setReg(CurrMO.getReg()); in pickBestRegisterForUndef()
170 MO.setReg(MaxClearanceReg); in pickBestRegisterForUndef()
H A DModuloSchedule.cpp344 O.setReg(ToReg); in replaceRegUsesAfterLoop()
1036 MO.setReg(NewReg); in updateInstruction()
1185 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
1191 UseOp.setReg(SplitReg); in rewriteScheduledInstr()
1334 MO.setReg(Reg); in rewrite()
1488 MI->getOperand(1).setReg(*InitReg); in phi()
1678 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
1692 NewMI->getOperand(0).setReg(R); in moveStageBetweenBlocks()
1693 NewMI->getOperand(1).setReg(OrigR); in moveStageBetweenBlocks()
1713 MO.setReg(R); in moveStageBetweenBlocks()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
H A DPPCVSXCopy.cpp114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
H A DPPCMIPeephole.cpp512 MO.setReg(PPC::NoRegister); in simplifyCode()
708 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
709 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
848 MI.getOperand(OpNo).setReg(ShiftOp1); in simplifyCode()
891 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
1812 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
1813 CMPI2->getOperand(2).setReg(Op1); in eliminateRedundantCompare()
1827 CMPI2->getOperand(I).setReg(SrcReg); in eliminateRedundantCompare()
1840 BI2->getOperand(1).setReg(NewVReg); in eliminateRedundantCompare()
1852 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); in eliminateRedundantCompare()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp372 Clone->getOperand(0).setReg(NewReg); in cloneSink()
390 MO.setReg(NewReg); in cloneSink()
398 MO.setReg(Reg); in updateReg()
400 Def->getOperand(0).setReg(Reg); in updateReg()
H A DWebAssemblyPeephole.cpp68 MO.setReg(NewReg); in maybeRewriteToDrop()
103 MO.setReg(NewReg); in maybeRewriteToFallthrough()
H A DWebAssemblyFixBrTableDefaults.cpp67 MI.getOperand(0).setReg(ExtMI->getOperand(1).getReg()); in fixBrTableIndex()
79 MI.getOperand(0).setReg(Reg32); in fixBrTableIndex()
H A DWebAssemblyExplicitLocals.cpp310 MI.getOperand(2).setReg(NewReg); in runOnMachineFunction()
359 Def.setReg(NewReg); in runOnMachineFunction()
417 MO.setReg(NewReg); in runOnMachineFunction()
H A DWebAssemblyReplacePhysRegs.cpp100 MO.setReg(VReg); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DAntiDepBreaker.h63 MI.getDebugOperand(0).setReg(NewReg); in UpdateDbgValue()
67 MI.getOperand(0).setReg(NewReg); in UpdateDbgValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp87 MI->getOperand(1).setReg(Tmp); in visitMBB()
93 MI->getOperand(0).setReg(Tmp); in visitMBB()
H A DSystemZPostRewrite.cpp118 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
125 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
223 SrcMO.setReg(DstReg); in selectMI()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp400 LoopPhi->getOperand(3).setReg(StartReg); in MergeLoopEnd()
401 LoopPhi->getOperand(1).setReg(DecReg); in MergeLoopEnd()
403 LoopPhi->getOperand(1).setReg(StartReg); in MergeLoopEnd()
404 LoopPhi->getOperand(3).setReg(DecReg); in MergeLoopEnd()
539 MI->getOperand(Idx + 2).setReg(LR); in ConvertTailPredLoop()
641 User.setReg(NewResult); in ReplaceRegisterUseWithVPNOT()
807 MO->setReg(LastVPNOTResult); in ReduceOldVCCRValueUses()
961 Instr.getOperand(PIdx + 1).setReg(LastVPTReg); in ReplaceConstByVPNOTs()
979 Instr.getOperand(PIdx + 1).setReg(NewVPR); in ReplaceConstByVPNOTs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp382 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
393 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
405 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
417 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
543 MO.setReg(High); in HexagonProcessInstruction()
555 MO.setReg(High); in HexagonProcessInstruction()
569 MO.setReg(High); in HexagonProcessInstruction()
602 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRVVInitUndef.cpp220 UseMO.setReg(LatestReg); in handleSubReg()
237 MO.setReg(NewReg); in fixupIllOperand()
264 UseMO.setReg(NewDest); in processBasicBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp398 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
437 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
471 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
472 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1408 MO.setReg(RegPair.first); in processInstruction()
1418 MO.setReg(RegPair.first); in processInstruction()
1429 MO.setReg(RegPair.first); in processInstruction()
1441 MO.setReg(RegPair.first); in processInstruction()
1755 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1781 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1786 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1798 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1803 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1815 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp137 LocalizedMI->getOperand(0).setReg(NewReg); in localizeInterBlock()
145 MOUse.setReg(NewVRegIt->second); in localizeInterBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h137 MI->getOperand(Operand + 2).setReg(0); in setDirectAddressInInstr()
139 MI->getOperand(Operand + 4).setReg(0); in setDirectAddressInInstr()
H A DX86FastPreTileConfig.cpp251 MO.setReg(StrideReg); in reload()
262 MO.setReg(TileReg); in reload()
419 MO.setReg(StrideReg); in convertPHI()
482 InMO->setReg(DefTileReg); in canonicalizePHIs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp157 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
247 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600EmitClauseMarkers.cpp163 Consts[i].first->setReg( in SubstituteKCacheBank()
167 Consts[i].first->setReg( in SubstituteKCacheBank()

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