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Searched refs:setDesc (Results 1 – 25 of 115) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
120 Def->setDesc(TII.get(NE_I64)); in runOnMachineFunction()
124 Def->setDesc(TII.get(EQ_I64)); in runOnMachineFunction()
160 Def->setDesc(TII.get(NE_F32)); in runOnMachineFunction()
164 Def->setDesc(TII.get(EQ_F32)); in runOnMachineFunction()
168 Def->setDesc(TII.get(NE_F64)); in runOnMachineFunction()
[all …]
H A DWebAssemblyRegStackify.cpp106 MI->setDesc(TII->get(WebAssembly::CONST_I32)); in convertImplicitDefToConstZero()
109 MI->setDesc(TII->get(WebAssembly::CONST_I64)); in convertImplicitDefToConstZero()
112 MI->setDesc(TII->get(WebAssembly::CONST_F32)); in convertImplicitDefToConstZero()
117 MI->setDesc(TII->get(WebAssembly::CONST_F64)); in convertImplicitDefToConstZero()
122 MI->setDesc(TII->get(WebAssembly::CONST_V128_I64x2)); in convertImplicitDefToConstZero()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
902 I.setDesc(TII.get(NewOpc)); in select()
958 I.setDesc(TII.get(COPY)); in select()
984 I.setDesc(TII.get(ARM::MOVi)); in select()
1030 I.setDesc(TII.get(COPY)); in select()
1099 I.setDesc(TII.get(NewOpc)); in select()
[all …]
H A DThumb2InstrInfo.cpp557 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
572 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
574 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
592 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
712 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
755 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp96 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
101 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
112 MI.setDesc(TII->get(Opcode)); in shortenOn0()
123 MI.setDesc(TII->get(Opcode)); in shortenOn01()
136 MI.setDesc(TII->get(Opcode)); in shortenOn001()
169 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
196 MI.setDesc(TII->get(Opcode)); in shortenFusedFPOp()
365 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
H A DSystemZPostRewrite.cpp88 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
90 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
139 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
141 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
216 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
H A DSystemZInstrInfo.cpp98 HighPartMI->setDesc(get(HighOpcode)); in splitMove()
99 LowPartMI->setDesc(get(LowOpcode)); in splitMove()
145 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
177 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
199 MI.setDesc(get(Opcode)); in expandRXYPseudo()
209 MI.setDesc(get(Opcode)); in expandLOCPseudo()
254 MI->setDesc(get(SystemZ::LG)); in expandLoadStackGuard()
680 UseMI.setDesc(get(NewUseOpc)); in FoldImmediate()
745 MI.setDesc(get(SystemZ::CondTrap)); in PredicateInstruction()
765 MI.setDesc(get(SystemZ::CallBRCL)); in PredicateInstruction()
[all …]
H A DSystemZElimCompare.cpp222 Branch->setDesc(TII->get(BRCT)); in convertToBRCT()
265 Branch->setDesc(TII->get(LATOpcode)); in convertToLoadAndTrap()
325 MI.setDesc(TII->get(ConvOpc)); in convertToLogical()
655 Branch->setDesc(TII->get(FusedOpcode)); in fuseCompareOperations()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp217 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
222 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
228 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
234 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
240 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
246 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
252 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
258 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
264 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
270 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
H A DSIFoldOperands.cpp346 MI->setDesc(TII->get(NegOpcode)); in tryFoldImmWithOpSel()
409 MI->setDesc(TII->get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
423 MI->setDesc(TII->get(NewMFMAOpc)); in updateOperand()
476 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
500 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
516 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
528 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
546 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
822 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
862 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
[all …]
H A DSIShrinkInstructions.cpp246 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
258 MI.setDesc(NewDesc); in shrinkScalarCompare()
367 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
480 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
539 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
806 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); in runOnMachineFunction()
848 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
868 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
871 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); in runOnMachineFunction()
H A DSIModeRegister.cpp181 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
189 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
198 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
206 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
H A DSIPreEmitPeephole.cpp196 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
224 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
234 MI.setDesc( in optimizeVccBranch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp251 MI.setDesc(get(VE::STrii)); in processSTQ()
271 MI.setDesc(get(VE::LDrii)); in processLDQ()
310 MI.setDesc(get(VE::STrii)); in processSTVM()
346 MI.setDesc(get(VE::LDrii)); in processLDVM()
408 MI.setDesc(get(VE::STrii)); in processSTVM512()
447 MI.setDesc(get(VE::LDrii)); in processLDVM512()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp82 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
95 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp343 I.setDesc(TII.get(X86::COPY)); in selectCopy()
586 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
622 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
674 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
726 I.setDesc(TII.get(NewOpc)); in selectConstant()
751 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
817 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
926 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1359 I.setDesc(TII.get(X86::VINSERTF128rr)); in selectInsert()
1562 I.setDesc(TII.get(X86::IMPLICIT_DEF)); in selectImplicitDefOrPHI()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CompressJumpTables.cpp148 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
154 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp139 MI.setDesc(TII->get(NewOpc)); in processInstruction()
154 MI.setDesc(TII->get(NewOpc)); in processInstruction()
168 MI.setDesc(TII->get(NewOpc)); in processInstruction()
190 MI.setDesc(TII->get(NewOpc)); in processInstruction()
202 MI.setDesc(TII->get(NewOpc)); in processInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp190 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
393 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
432 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) in combineRestoreOR()
469 RestoreMI->setDesc(TII->get(SP::RESTOREri)); in combineRestoreSETHIi()
H A DSparcRegisterInfo.cpp202 MI.setDesc(TII.get(SP::STDFri)); in eliminateFrameIndex()
215 MI.setDesc(TII.get(SP::LDDFri)); in eliminateFrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp93 MI->setDesc(TII->get(PPC::BCCLR)); in processBlock()
110 MI->setDesc( in processBlock()
H A DPPCInstrInfo.cpp2200 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2208 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2216 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2716 MI->setDesc(NewDesc); in optimizeCompareInstr()
2806 SrcMI->setDesc(NewDesc); in optimizeCmpPostRA()
3053 MI.setDesc(get(Opcode)); in expandVSXMemPseudo()
3139 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
3150 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
3159 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
3184 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFoldMasks.cpp121 MI.setDesc(TII->get(NewOpc)); in convertVMergeToVMv()
160 MI.setDesc(MCID); in convertToUnmasked()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp530 MI.setDesc(TII.get(TargetOpcode::PHI)); in select()
672 MI.setDesc(TII.get(RISCV::PseudoBRIND)); in select()
681 MI.setDesc(TII.get(RISCV::ADDI)); in select()
723 MI.setDesc(TII.get(RISCV::BuildPairF64Pseudo)); in selectMergeValues()
739 MI.setDesc(TII.get(RISCV::SplitF64Pseudo)); in selectUnmergeValues()
765 MI.setDesc(TII.get(TargetOpcode::G_ADD)); in preISelLower()
773 MI.setDesc(TII.get(TargetOpcode::G_AND)); in preISelLower()
882 MI.setDesc(TII.get(RISCV::COPY)); in selectCopy()
901 MI.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); in selectImplicitDef()
979 MI.setDesc(TII.get(RISCV::PseudoLLA)); in selectAddr()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp379 MIB->setDesc(get(Move)); in ExpandMOVX_RR()
456 MIB->setDesc(Desc); in ExpandMOVSZX_RM()
495 MIB->setDesc(get(M68k::MOV16cd)); in ExpandCCR()
498 MIB->setDesc(get(M68k::MOV16dc)); in ExpandCCR()
566 MIB->setDesc(Desc); in Expand2AddrUndef()

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