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Searched refs:reg_base (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/sys/arm64/broadcom/brcmmdio/
H A Dmdio_mux_iproc.c96 struct resource * reg_base; member
162 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); in brcm_iproc_switch()
174 val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in iproc_mdio_wait_for_idle()
203 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0); in brcm_iproc_mdio_op()
204 bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in brcm_iproc_mdio_op()
209 param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); in brcm_iproc_mdio_op()
217 bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg); in brcm_iproc_mdio_op()
219 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op); in brcm_iproc_mdio_op()
316 if (sc->reg_base == NULL) { in brcm_iproc_mdio_attach()
389 if (sc->reg_base != NULL) { in brcm_iproc_mdio_detach()
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/freebsd-14.2/sys/contrib/dev/athk/ath11k/
H A Dhal.c276 u32 reg_base; in ath11k_hal_srng_dst_hw_init() local
281 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_dst_hw_init()
289 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_dst_hw_init()
332 ath11k_hif_write32(ab, reg_base, 0); in ath11k_hal_srng_dst_hw_init()
355 u32 reg_base; in ath11k_hal_srng_src_hw_init() local
360 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_src_hw_init()
368 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_src_hw_init()
372 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_src_hw_init()
437 ath11k_hif_write32(ab, reg_base, 0); in ath11k_hal_srng_src_hw_init()
967 u32 reg_base; in ath11k_hal_srng_setup() local
[all …]
/freebsd-14.2/sys/contrib/dev/athk/ath12k/
H A Dhal.c1259 u32 reg_base; in ath12k_hal_srng_dst_hw_init() local
1264 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_dst_hw_init()
1271 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_dst_hw_init()
1312 ath12k_hif_write32(ab, reg_base, 0); in ath12k_hal_srng_dst_hw_init()
1335 u32 reg_base; in ath12k_hal_srng_src_hw_init() local
1340 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_src_hw_init()
1347 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_src_hw_init()
1351 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_src_hw_init()
1400 ath12k_hif_write32(ab, reg_base, 0); in ath12k_hal_srng_src_hw_init()
1905 u32 reg_base; in ath12k_hal_srng_setup() local
[all …]
/freebsd-14.2/sys/dev/vnic/
H A Dthunder_mdio.c143 bus_read_8((sc)->reg_base, (reg))
146 bus_write_8((sc)->reg_base, (reg), (val))
159 sc->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in thunder_mdio_attach()
161 if (sc->reg_base == NULL) { in thunder_mdio_attach()
182 if (sc->reg_base != NULL) { in thunder_mdio_detach()
184 sc->reg_base); in thunder_mdio_detach()
H A Dthunder_bgx.c147 bgx->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in thunder_bgx_attach()
149 if (bgx->reg_base == NULL) { in thunder_bgx_attach()
155 bgx->bgx_id = (rman_get_start(bgx->reg_base) >> BGX_NODE_ID_SHIFT) & in thunder_bgx_attach()
157 bgx->bgx_id += nic_get_node_id(bgx->reg_base) * MAX_BGX_PER_CN88XX; in thunder_bgx_attach()
183 rman_get_rid(bgx->reg_base), bgx->reg_base); in thunder_bgx_attach()
206 rman_get_rid(bgx->reg_base), bgx->reg_base); in thunder_bgx_detach()
221 return (bus_read_8(bgx->reg_base, addr)); in bgx_reg_read()
231 bus_write_8(bgx->reg_base, addr, val); in bgx_reg_write()
241 bus_write_8(bgx->reg_base, addr, val | bus_read_8(bgx->reg_base, addr)); in bgx_reg_modify()
H A Dnic_main.c102 struct resource * reg_base; /* Register start address */ member
209 nic->node = nic_get_node_id(nic->reg_base); in nicpf_attach()
341 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in nicpf_alloc_res()
343 if (nic->reg_base == NULL) { in nicpf_alloc_res()
362 if (nic->reg_base != NULL) { in nicpf_free_res()
364 rman_get_rid(nic->reg_base), nic->reg_base); in nicpf_free_res()
374 bus_write_8(nic->reg_base, offset, val); in nic_reg_write()
382 val = bus_read_8(nic->reg_base, offset); in nic_reg_read()
H A Dnicvf_main.c200 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in nicvf_attach()
202 if (nic->reg_base == NULL) { in nicvf_attach()
270 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), in nicvf_attach()
271 nic->reg_base); in nicvf_attach()
291 if (nic->reg_base != NULL) { in nicvf_detach()
293 rman_get_rid(nic->reg_base), nic->reg_base); in nicvf_detach()
798 bus_write_8(nic->reg_base, offset, val); in nicvf_reg_write()
805 return (bus_read_8(nic->reg_base, offset)); in nicvf_reg_read()
813 bus_write_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT), val); in nicvf_queue_reg_write()
821 return (bus_read_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT))); in nicvf_queue_reg_read()
H A Dthunder_mdio_var.h53 struct resource * reg_base; member
H A Dthunder_bgx_var.h52 struct resource * reg_base; member
H A Dnic.h310 struct resource *reg_base; member
/freebsd-14.2/sys/contrib/dev/rtw89/
H A Dmac.h829 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) in rtw89_mac_reg_by_idx() argument
831 return band == 0 ? reg_base : (reg_base + 0x2000); in rtw89_mac_reg_by_idx()
987 u32 reg_base, u32 *cr);
1015 u32 reg_base, u32 *val) in rtw89_mac_txpwr_read32() argument
1019 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) in rtw89_mac_txpwr_read32()
1028 u32 reg_base, u32 val) in rtw89_mac_txpwr_write32() argument
1032 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) in rtw89_mac_txpwr_write32()
1041 u32 reg_base, u32 mask, u32 val) in rtw89_mac_txpwr_write32_mask() argument
1045 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) in rtw89_mac_txpwr_write32_mask()
H A Dmac.c3927 u32 reg_base; in rtw89_mac_port_cfg_bss_color() local
3932 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; in rtw89_mac_port_cfg_bss_color()
3933 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); in rtw89_mac_port_cfg_bss_color()
4741 u32 reg_base, u32 *cr) in rtw89_mac_get_txpwr_cr() argument
4745 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); in rtw89_mac_get_txpwr_cr()
/freebsd-14.2/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt106 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
171 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
172 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
/freebsd-14.2/sys/arm64/iommu/
H A Dsmmu.c940 uint64_t reg_base; in smmu_init_strtab_2lvl() local
982 reg_base = base & STRTAB_BASE_ADDR_M; in smmu_init_strtab_2lvl()
983 KASSERT(reg_base == base, ("bad allocation 3")); in smmu_init_strtab_2lvl()
984 reg_base |= STRTAB_BASE_RA; in smmu_init_strtab_2lvl()
985 strtab->base = reg_base; in smmu_init_strtab_2lvl()
/freebsd-14.2/sys/contrib/dev/mediatek/mt76/
H A Ddma.c667 q->wed_regs = wed->tx_ring[ring].reg_base; in mt76_dma_wed_setup()
678 q->wed_regs = wed->txfree_ring.reg_base; in mt76_dma_wed_setup()
683 q->wed_regs = wed->rx_ring[ring].reg_base; in mt76_dma_wed_setup()
/freebsd-14.2/sys/dev/bnxt/bnxt_en/
H A Dif_bnxt.c1653 u32 reg_base = 0xffffffff; in bnxt_map_fw_health_regs() local
1664 if (reg_base == 0xffffffff) in bnxt_map_fw_health_regs()
1665 reg_base = reg & BNXT_GRC_BASE_MASK; in bnxt_map_fw_health_regs()
1666 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) in bnxt_map_fw_health_regs()
1672 if (reg_base == 0xffffffff) in bnxt_map_fw_health_regs()
1675 __bnxt_map_fw_health_reg(bp, reg_base); in bnxt_map_fw_health_regs()
/freebsd-14.2/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
H A Dtegra210.dtsi1320 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1321 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dtegra124.dtsi921 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
922 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */