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Searched refs:regClass (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td197 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
243 def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
253 (outs regClass:$vdst),
256 !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
280 def "" : FLAT_Store_Pseudo<opName, regClass, 1>,
282 def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
334 def "" : FLAT_Global_Store_AddTid_Pseudo<opName, regClass>,
380 (outs getLdStRegisterOperand<regClass>.ret:$vdst),
449 def "" : FLAT_Scratch_Store_Pseudo<opName, regClass>,
451 def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>,
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H A DSIWholeQuadMode.cpp1508 const TargetRegisterClass *regClass = in lowerCopyInstrs() local
1510 if (TRI->isVGPRClass(regClass)) { in lowerCopyInstrs()
1511 const unsigned MovOp = TII->getMovOpcode(regClass); in lowerCopyInstrs()
H A DSIInstrInfo.cpp9491 const TargetRegisterClass *regClass = in getInstructionUniformity() local
9493 return RI.isSGPRClass(regClass) ? InstructionUniformity::AlwaysUniform in getInstructionUniformity()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp122 int16_t regClass = Desc.operands()[OpNo].RegClass; in getRegNumForOperand() local
123 switch (regClass) { in getRegNumForOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td123 class MemOperand<RegisterClass regClass> : RegisterOperand<regClass>{