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/freebsd-14.2/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,smsm.txt4 information between the processors in a Qualcomm SoC. Each processor is
5 assigned 32 bits of state that can be modified. A processor can through a
7 certain bit owned by a certain remote processor.
19 signaling the N:th remote processor
27 Definition: identifier of the local processor in the list of hosts, or
29 matrix representing the local processor
45 processor's state bits or the local processors bits. The node names are not
63 to belong to a remote processor
73 Definition: one entry specifying remote IRQ used by the remote processor
79 wireless processor, defined from the 8974 apps processor's point-of-view. It
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H A Dqcom,smsm.yaml16 information between the processors in a Qualcomm SoC. Each processor is
17 assigned 32 bits of state that can be modified. A processor can through a
19 certain bit owned by a certain remote processor.
32 Identifier of the local processor in the list of hosts, or in other words
34 processor.
49 remote processor.
56 remote processor's state bits or the local processors bits. The node
66 belong to a remote processor.
74 One entry specifying remote IRQ used by the remote processor to
115 # the wireless processor, defined from the 8974 apps processor's
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H A Dqcom,smd.txt15 processor of some sort - or in SMD language an "edge". The name of the edges
22 Definition: should specify the IRQ used by the remote processor to
23 signal this processor about communication related updates
35 signaling the remote processor:
43 Definition: the identifier of the remote processor in the smd channel
49 Definition: the identifier for the remote processor as known by the rest
H A Dqcom,apr.yaml14 communication between Application processor and QDSP. APR/GPR is mainly
31 Selects the processor domain for apr
36 5 = Application processor Domain
46 Selects the processor domain for apr
51 5 = Application processor Domain
54 Selects the processor domain for gpr
/freebsd-14.2/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,mu-msi.yaml16 for one processor (A side) to signal the other processor (B side) using
45 - const: processor-a-side
46 - const: processor-b-side
62 - const: processor-a-side
63 - const: processor-b-side
94 reg-names = "processor-a-side", "processor-b-side";
98 power-domain-names = "processor-a-side", "processor-b-side";
/freebsd-14.2/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,omap-remoteproc.yaml21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
30 processor and to communicate with the remote processor. The various properties
54 for this remote processor to access any external RAM memory or
58 sub-modules within the processor sub-system (eg: DRA7 DSPs),
75 Main functional clock for the remote processor
81 Reset handles for the remote processor
150 processor sub-system is running in SMP mode, or one per
151 core in the processor sub-system. This can also be used
166 serve as Watchdog timers for the processor cores. This
167 will usually be one per executing processor core, even
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H A Dxlnx,zynqmp-r5fss.yaml7 title: Xilinx R5F processor subsystem
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
27 The RPU MPCore can operate in split mode (Dual-processor performance), Safety
30 core 1 runs normally). The processor does not support dynamic configuration.
31 Switching between modes is only permitted immediately after a processor reset.
44 Each processor includes separate L1 instruction and data caches and
50 per processor. In lock-step mode, the processor has access to 256KB of
91 the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
H A Drenesas,rcar-rproc.yaml7 title: Renesas R-Car remote processor controller
15 R-Car gen3 family may have a realtime processor, this processor shares peripheral
16 and RAM with the host processor with the same address map.
32 the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
H A Dst-rproc.txt7 the bootloader starts a co-processor, the primary OS must detect its state
17 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
18 - clock-frequency Clock frequency to set co-processor at if the bootloader
21 for the co-processor
H A Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
56 the remote processor to the host processor. The values should
67 stack. This will be used to interrupt the remote processor.
H A Dti,k3-dsp-rproc.yaml14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
21 TMS320C71x CorePac processor.
25 host processor (Arm CorePac) to perform the device management of the remote
26 processor and to communicate with the remote processor.
58 communication with the remote processor. This property should match
H A Dfsl,imx-rproc.yaml10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
55 resource table, vring region and others used by remote processor.
66 processor automatically.
71 Specify CPU entry address for SCU enabled processor.
76 This property is to specify the resource id of the remote processor in SoC
H A Dwkup_m3_rproc.txt4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
6 that cannot be controlled from the MPU. This CM3 processor requires a firmware
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
29 booting the wkup_m3 remote processor.
/freebsd-14.2/contrib/ntp/scripts/ntpsweep/
H A Dntpsweep.in62 Host st offset(s) version system processor
105 my $processor = "";
117 my $vars = ntp_read_vars(0, [qw(processor system daemon_version)], $host) || {};
120 $processor = $vars->{processor};
136 $processor =~ s/unknown//;
156 (substr $system, 0, 12), (substr $processor, 0, 9);
/freebsd-14.2/contrib/expat/xmlwf/
H A Dunixfilemap.c61 void (*processor)(const void *, size_t, const tchar *, void *arg), in filemap()
92 processor(&c, 0, name, arg); in filemap()
103 processor(p, nbytes, name, arg); in filemap()
H A Dreadfilemap.c88 void (*processor)(const void *, size_t, const tchar *, void *arg), in filemap()
120 processor(&c, 0, name, arg); in filemap()
143 processor(p, nbytes, name, arg); in filemap()
H A Dwin32filemap.c58 void (*processor)(const void *, size_t, const TCHAR *, void *arg), in filemap()
85 processor(&c, 0, name, arg); in filemap()
102 processor(p, size, name, arg); in filemap()
H A Dfilemap.h49 void (*processor)(const void *, size_t, const wchar_t *, void *arg),
53 void (*processor)(const void *, size_t, const char *, void *arg),
/freebsd-14.2/sys/contrib/device-tree/Bindings/mailbox/
H A Domap-mailbox.txt6 various processor subsystems and is connected on an interconnect bus. The
12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
57 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
81 used for the communication between the host processor and a remote processor.
99 multiple interrupt lines connected to the MPU processor.
109 processor on AM33xx/AM43xx SoCs.
113 A device needing to communicate with a target processor device should specify
H A Dti,omap-mailbox.yaml15 external to the various processor subsystems and is connected on an
21 controller within a processor subsystem, and there can be more than one line
22 going to a specific processor's interrupt controller. The interrupt line
35 lines can also be routed to different processor sub-systems on DRA7xx as they
40 to different processor subsystems over a limited number of common interrupt
54 A device needing to communicate with a target processor device should specify
91 receive messages between the host processor and a remote processor. Each
110 communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.
134 interrupts reaching the main processor. An interrupt-parent property
136 Interrupt Router before reaching the main processor's GIC.
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/freebsd-14.2/sys/contrib/device-tree/Bindings/arm/keystone/
H A Dti,k3-sci-common.yaml15 resets, interrupts etc. The communication with that processor is performed
42 - description: TI-SCI processor id for the remote processor device
43 - description: TI-SCI host id to which processor control ownership
/freebsd-14.2/sys/contrib/device-tree/Bindings/hwmon/
H A Dibm,occ-hwmon.yaml7 title: IBM On-Chip Controller (OCC) accessed from a service processor
13 The POWER processor On-Chip Controller (OCC) helps manage power and
14 thermals for the system. A service processor or baseboard management
/freebsd-14.2/sys/contrib/device-tree/Bindings/timer/
H A Dsamsung,exynos4210-mct.yaml52 Indicates that the hardware requires that this processor share the
53 free-running counter with a different (main) processor.
60 List of indices of local timers usable from this processor.
76 For MCT block that uses a per-processor interrupt for local timers, such
79 per processor interrupt.
198 // a per-processor interrupt to handle them. Only one first local
218 // a per-processor interrupt to handle them. All the local timer
/freebsd-14.2/sys/contrib/device-tree/Bindings/reserved-memory/
H A Dqcom,cmd-db.yaml11 resource address for a system resource managed by a remote processor. The data
12 is stored in a shared memory region and is loaded by the remote processor.
17 remote processor and made available in the shared memory.
H A Dqcom,cmd-db.txt5 resource address for a system resource managed by a remote processor. The data
6 is stored in a shared memory region and is loaded by the remote processor.
11 remote processor and made available in the shared memory.

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