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Searched refs:postdiv1 (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/sys/arm64/rockchip/clk/
H A Drk3399_pmucru.c144 .postdiv1 = 1,
152 .postdiv1 = 1,
160 .postdiv1 = 1,
168 .postdiv1 = 1,
176 .postdiv1 = 1,
184 .postdiv1 = 1,
192 .postdiv1 = 1,
200 .postdiv1 = 1,
208 .postdiv1 = 1,
216 .postdiv1 = 1,
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H A Drk_clk_pll.c241 reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT; in rk3066_clk_pll_set_freq()
383 uint32_t postdiv1, postdiv2, frac; in rk3328_clk_pll_recalc() local
395 postdiv1 = (raw1 & RK3328_CLK_PLL_POSTDIV1_MASK) >> RK3328_CLK_PLL_POSTDIV1_SHIFT; in rk3328_clk_pll_recalc()
414 *freq = rate / postdiv1 / postdiv2; in rk3328_clk_pll_recalc()
458 reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) | in rk3328_clk_pll_set_freq()
590 uint32_t postdiv1, postdiv2, fracdiv; in rk3399_clk_pll_recalc() local
626 postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) in rk3399_clk_pll_recalc()
640 dprintf("postdiv1: %d\n", postdiv1); in rk3399_clk_pll_recalc()
657 *freq = foutvco / postdiv1 / postdiv2; in rk3399_clk_pll_recalc()
703 reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT; in rk3399_clk_pll_set_freq()
H A Drk_clk_pll.h37 uint32_t postdiv1; member
H A Drk3288_cru.c368 .postdiv1 = _post, \
H A Drk3328_cru.c576 .postdiv1 = _post1, \
H A Drk3399_cru.c553 .postdiv1 = _post1, \
H A Drk3568_cru.c60 .postdiv1 = _post1, \