Searched refs:isZeroExtended (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 131 bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended() function
169 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 609 bool isZeroExtended(const unsigned Reg, in isZeroExtended() function
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| H A D | PPCMIPeephole.cpp | 282 if (TII->isZeroExtended(Reg, MRI)) in getKnownLeadingZeroCount()
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| H A D | PPCInstrInfo.cpp | 2411 if (isZeroExtended(SrcReg, MRI)) { in optimizeCompareInstr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9462 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
9604 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9624 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9625 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4549 static bool isZeroExtended(SDValue N, SelectionDAG &DAG) { in isZeroExtended() function
4572 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
4651 bool IsN0ZExt = isZeroExtended(N0, DAG); in selectUmullSmull()
4652 bool IsN1ZExt = isZeroExtended(N1, DAG); in selectUmullSmull()
17142 isZeroExtended(N0, DAG))) in performMulCombine()
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