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Searched refs:isVirtual (Results 1 – 25 of 270) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
186 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
207 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
238 if (Reg0.isVirtual()) { in runOnMachineFunction()
H A DHexagonGenPredicate.cpp138 if (!R.isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
216 if (RD.R.isVirtual()) in collectPredicateGPR()
248 assert(Reg.R.isVirtual()); in getPredRegFor()
474 if (!DR.R.isVirtual()) in eliminatePredCopies()
476 if (!SR.R.isVirtual()) in eliminatePredCopies()
/freebsd-14.2/contrib/llvm-project/clang/lib/AST/
H A DInheritViz.cpp100 if (!Base.isVirtual()) in WriteNode()
104 WriteNode(Base.getType(), Base.isVirtual()); in WriteNode()
110 WriteNodeReference(Base.getType(), Base.isVirtual()); in WriteNode()
113 if (Base.isVirtual()) { in WriteNode()
H A DVTTBuilder.cpp64 if (I.isVirtual()) in LayoutSecondaryVTTs()
109 if (I.isVirtual()) { in LayoutSecondaryVirtualPointers()
161 if (I.isVirtual()) { in LayoutVirtualVTTs()
H A DCXXInheritance.cpp187 if (BaseSpec.isVirtual()) { in lookupInBases()
204 if (BaseSpec.isVirtual()) in lookupInBases()
332 if (!PE.Base->isVirtual()) in lookupInBases()
377 return Specifier->isVirtual() && in FindVirtualBaseClass()
526 if (Overriders.empty() && !Base.isVirtual()) { in Collect()
540 if (Base.isVirtual()) { in Collect()
570 if (!M->isVirtual()) in Collect()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h106 assert(virtReg.isVirtual()); in getPhys()
121 assert(virtReg.isVirtual()); in getShape()
132 assert(virtReg.isVirtual()); in clearVirt()
188 assert(virtReg.isVirtual()); in getStackSlot()
H A DMachineRegisterInfo.h115 if (RegNo.isVirtual()) in getRegUseDefListHead()
121 if (RegNo.isVirtual()) in getRegUseDefListHead()
231 assert(VReg.isVirtual() && "Must pass a VReg"); in shouldTrackSubRegLiveness()
762 if (Reg.isVirtual() && VRegToType.inBounds(Reg)) in getType()
795 assert(VReg.isVirtual()); in setRegAllocationHint()
804 assert(VReg.isVirtual()); in addRegAllocationHint()
824 assert(VReg.isVirtual()); in getRegAllocationHint()
833 assert(VReg.isVirtual()); in getSimpleHint()
842 assert(VReg.isVirtual()); in getRegAllocationHints()
1242 if (RegUnit.isVirtual()) { in PSetIterator()
H A DRegister.h78 assert(Reg.isVirtual() && "Not a virtual register"); in virtReg2Index()
91 constexpr bool isVirtual() const { return isVirtualRegister(Reg); } in isVirtual() function
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGCall.h173 if (isVirtual()) in getAbstractInfo()
188 bool isVirtual() const { in isVirtual() function
192 assert(isVirtual()); in getVirtualCallExpr()
196 assert(isVirtual()); in getVirtualMethodDecl()
200 assert(isVirtual()); in getThisAddress()
204 assert(isVirtual()); in getVirtualFunctionType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCSE.cpp183 if (!Reg.isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
190 if (!SrcReg.isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
299 if (Reg.isVirtual()) in hasLivePhysRegDefUses()
319 if (Reg.isVirtual()) in hasLivePhysRegDefUses()
394 if (MOReg.isVirtual()) in PhysRegDefsReach()
453 if (CSReg.isVirtual() && Reg.isVirtual()) { in isProfitableToCSE()
489 if (MO.getReg().isVirtual()) { in isProfitableToCSE()
653 assert(OldReg.isVirtual() && NewReg.isVirtual() && in ProcessBlockCSE()
816 if (MO.isReg() && !MO.getReg().isVirtual()) { in isPRECandidate()
H A DDetectDeadLanes.cpp113 if (!MOReg.isVirtual()) in addUsedLanesOnOperand()
137 if (!MO.isReg() || !MO.getReg().isVirtual()) in transferUsedLanesStep()
205 if (!DefReg.isVirtual()) in transferDefinedLanesStep()
306 assert(MOReg.isVirtual()); in determineInitialDefinedLanes()
350 if (DefReg.isVirtual()) { in determineInitialUsedLanes()
434 if (!DefReg.isVirtual()) in isUndefInput()
446 if (MOReg.isVirtual()) { in isUndefInput()
507 if (!Reg.isVirtual()) in modifySubRegisterOperandStatus()
H A DMIRCanonicalizerPass.cpp158 if (MO.getReg().isVirtual()) in rescheduleCanonically()
175 if (!MO.isReg() || !MO.getReg().isVirtual()) in rescheduleCanonically()
188 if (!II->getOperand(i).getReg().isVirtual()) in rescheduleCanonically()
310 if (!Dst.isVirtual()) in propagateLocalCopies()
312 if (!Src.isVirtual()) in propagateLocalCopies()
H A DRegAllocFast.cpp419 assert(Reg.isVirtual()); in shouldAllocateRegister()
833 assert(Reg.isVirtual()); in traceCopyChain()
956 assert(VirtReg.isVirtual() && "Expected virtreg"); in allocVirtRegUndef()
1124 if (Hint.isVirtual()) { in useVirtReg()
1225 assert(VirtReg.isVirtual() && "Bad map key"); in dumpState()
1242 if (Reg.isVirtual()) { in addRegClassDefCounts()
1373 if (Reg.isVirtual()) { in allocateInstruction()
1449 if (Reg.isVirtual()) { in allocateInstruction()
1484 if (Reg.isVirtual()) { in allocateInstruction()
1581 if (Reg.isVirtual()) { in allocateInstruction()
[all …]
H A DVirtRegMap.cpp86 assert(virtReg.isVirtual() && Register::isPhysicalRegister(physReg)); in assignVirt2Phys()
113 if (Hint.isVirtual()) in hasPreferredPhys()
122 if (Hint.second.isVirtual()) in hasKnownPreference()
128 assert(virtReg.isVirtual()); in assignVirt2StackSlot()
136 assert(virtReg.isVirtual()); in assignVirt2StackSlot()
417 if (DstReg.isVirtual()) in handleIdentityCopy()
550 if (!MO.isReg() || !MO.getReg().isVirtual()) in rewrite()
H A DMachineCombiner.cpp156 if (MO.isReg() && MO.getReg().isVirtual()) in getOperandDef()
187 if (Src.isVirtual() && Dst.isVirtual()) { in isTransientMI()
193 if (Src.isVirtual()) in isTransientMI()
222 if (!MO.getReg().isVirtual()) in getDepth()
275 if (!MO.getReg().isVirtual()) in getLatency()
H A DMachineSink.cpp329 if (!SrcReg.isVirtual() || !DstReg.isVirtual() || in PerformTrivialForwardCoalescing()
392 if (Reg.isVirtual()) { in PerformSinkAndFold()
443 if (DstReg.isVirtual()) { in PerformSinkAndFold()
540 if (Register R = MaybeAM.BaseReg; R.isValid() && R.isVirtual()) in PerformSinkAndFold()
542 if (Register R = MaybeAM.ScaledReg; R.isValid() && R.isVirtual()) in PerformSinkAndFold()
593 assert(Reg.isVirtual() && "Only makes sense for vregs"); in AllUsesDominatedByBlock()
868 if (MO.isReg() && MO.getReg().isVirtual()) in ProcessDbgInst()
1352 if (Reg.isVirtual() != SrcMO->getReg().isVirtual()) in attemptDebugCopyProp()
1357 bool arePhysRegs = !Reg.isVirtual(); in attemptDebugCopyProp()
1716 if (!MO.getReg().isVirtual()) in SinkInstruction()
[all …]
H A DTwoAddressInstructionPass.cpp332 if (Reg.isVirtual()) in isPlainlyKilled()
459 while (Reg.isVirtual()) { in getMappedReg()
490 if (ToReg.isVirtual()) in removeMapRegEntry()
526 if (!Dst || Dst.isVirtual()) in removeClobberedSrcRegMap()
542 if (!Reg || Reg.isVirtual()) in removeClobberedSrcRegMap()
1254 if (regA.isVirtual()) in tryInstructionTransform()
1371 if (MO.isReg() && MO.getReg().isVirtual()) { in tryInstructionTransform()
1461 if (DstReg.isVirtual()) { in collectTiedOperands()
1532 if (RegA.isVirtual()) { in processTiedPairs()
1555 if (RegA.isVirtual()) { in processTiedPairs()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp138 if (Reg.isVirtual()) in usesRegClass()
193 if (!Reg.isVirtual()) in eraseInstrWithNoUses()
215 if (!DefReg.isVirtual()) { in eraseInstrWithNoUses()
249 if (DPRReg.isVirtual() && SPRReg.isVirtual()) { in optimizeSDPattern()
299 if (!OpReg.isVirtual()) in optimizeSDPattern()
343 if (!MI->getOperand(1).getReg().isVirtual()) in elideCopies()
369 if (!Reg.isVirtual()) { in elideCopiesAndPHIs()
378 if (!MI->getOperand(1).getReg().isVirtual()) in elideCopiesAndPHIs()
H A DMLxExpansionPass.cpp100 if (Reg.isVirtual()) { in getAccDefMI()
106 if (Reg.isVirtual()) { in getAccDefMI()
156 if (SrcReg.isVirtual()) { in hasLoopHazard()
164 if (Reg.isVirtual()) { in hasLoopHazard()
170 if (Reg.isVirtual()) { in hasLoopHazard()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp109 return RA.getReg().isVirtual() || in checkOpConstraints()
119 if (!RT.getReg().isVirtual()) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
H A DPPCMIPeephole.cpp213 if (!Reg.isVirtual()) in getVRegDefOrNull()
356 if (!RegOp.isVirtual()) in collectUnprimedAccPHIs()
549 if (!Src.isVirtual() || !Dst.isVirtual()) in simplifyCode()
791 if (!TrueReg.isVirtual()) in simplifyCode()
801 if (!ConvReg.isVirtual()) in simplifyCode()
858 if (!TrueReg.isVirtual()) in simplifyCode()
869 if (!DefsReg1.isVirtual() || !DefsReg2.isVirtual()) in simplifyCode()
1069 if (!SrcReg.isVirtual()) in simplifyCode()
1085 if (CopyReg.isVirtual()) in simplifyCode()
1881 if (!SrcReg.isVirtual()) in emitRLDICWhenLoweringJumpTables()
[all …]
/freebsd-14.2/contrib/llvm-project/clang/lib/AST/Interp/
H A DFunction.cpp47 bool Function::isVirtual() const { in isVirtual() function in Function
49 return M->isVirtual(); in isVirtual()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp80 if (DstReg.isVirtual() && in visitMBB()
90 else if (SrcReg.isVirtual() && in visitMBB()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp100 if (Reg.isVirtual()) { in foldImmediates()
151 assert(!Reg.isVirtual() && "Prior checks should ensure we only shrink " in shouldShrinkTrue16()
530 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
569 } else if (MO.getReg() == Reg && Reg.isVirtual()) { in instAccessReg()
736 if (T.isVirtual() && MRI->use_nodbg_empty(T)) { in matchSwap()
836 if (Dest->getReg().isVirtual() && Src0->isReg()) { in runOnMachineFunction()
932 if (DstReg.isVirtual()) { in runOnMachineFunction()
958 if (SReg.isVirtual()) { in runOnMachineFunction()
974 if (SDst->getReg().isVirtual()) in runOnMachineFunction()
984 if (Src2->getReg().isVirtual()) in runOnMachineFunction()
H A DSIOptimizeExecMaskingPreRA.cpp96 if (Reg.isVirtual()) in isDefBetween()
220 if (CCReg.isVirtual()) { in optimizeVcndVcmpPair()
232 LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) : nullptr; in optimizeVcndVcmpPair()
457 if (SavedExec.isVirtual() && MRI->hasOneNonDBGUse(SavedExec)) { in runOnMachineFunction()
478 if (Reg.isVirtual()) { in runOnMachineFunction()

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