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Searched refs:isShiftedUInt (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td24 defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
27 defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
75 defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>;
84 defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
90 defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
93 defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
96 defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>;
99 defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
102 defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>;
105 defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>;
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H A DHexagonInstrInfo.cpp2799 return isShiftedUInt<6,1>(Offset); in isValidOffset()
2804 return isShiftedUInt<6,2>(Offset); in isValidOffset()
2900 return isShiftedUInt<6,1>(Offset); in isValidOffset()
2906 return isShiftedUInt<6,2>(Offset); in isValidOffset()
2912 return isShiftedUInt<6,3>(Offset); in isValidOffset()
3954 isShiftedUInt<3,1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3976 isShiftedUInt<5,3>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4039 isShiftedUInt<5,2>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4044 isShiftedUInt<4,2>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4072 isShiftedUInt<3,1>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp124 return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset) in compressibleSPOffset()
125 : isShiftedUInt<6, 3>(Offset); in compressibleSPOffset()
H A DRISCVInstrInfoZc.td19 ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
28 return isShiftedUInt<1, 1>(Imm);
72 return isShiftedUInt<2, 4>(Imm);
H A DRISCVInstrInfoC.td100 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
109 return isShiftedUInt<5, 2>(Imm);
115 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
124 return isShiftedUInt<6, 2>(Imm);
130 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
139 return isShiftedUInt<5, 3>(Imm);
162 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
171 return isShiftedUInt<6, 3>(Imm);
179 [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
188 return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
H A DRISCVInstrInfo.cpp1987 Ok = isShiftedUInt<1, 1>(Imm); in verifyInstruction()
1990 Ok = isShiftedUInt<5, 2>(Imm); in verifyInstruction()
1993 Ok = isShiftedUInt<6, 2>(Imm); in verifyInstruction()
1996 Ok = isShiftedUInt<5, 3>(Imm); in verifyInstruction()
2002 Ok = isShiftedUInt<6, 3>(Imm); in verifyInstruction()
2008 Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0); in verifyInstruction()
H A DRISCVInstrInfoXTHead.td723 return isShiftedUInt<2, 3>(Imm);
732 return isShiftedUInt<2, 4>(Imm);
H A DRISCVISelLowering.cpp13813 if ((Offset1 + 4 == Offset2) && isShiftedUInt<2, 3>(Offset1)) in performMemPairCombine()
13817 if ((Offset1 + 8 == Offset2) && isShiftedUInt<2, 4>(Offset1)) in performMemPairCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td114 ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
333 return isShiftedUInt<5, 0>(Imm);
345 return isShiftedUInt<5, 1>(Imm);
353 return isShiftedUInt<5, 2>(Imm);
364 return isShiftedUInt<7, 2>(Imm);
373 return isShiftedUInt<8, 0>(Imm);
381 return isShiftedUInt<8, 2>(Imm);
393 return isShiftedUInt<12, 0>(Imm);
401 return isShiftedUInt<12, 1>(Imm);
409 return isShiftedUInt<12, 2>(Imm);
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H A DCSKYInstrInfo.cpp241 } else if (isShiftedUInt<16, 16>(Val)) { in movImm()
H A DCSKYFrameLowering.cpp555 } else if (!STI.hasE2() && isShiftedUInt<7, 2>(std::abs(Val))) { in adjustReg()
H A DCSKYInstrInfoF1.td68 "return isShiftedUInt<"#width#", "#shift#">(N->getValueAPF().bitcastToAPInt().getZExtValue());">;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h205 return isShiftedUInt<N, S>(minConstant(MCI, Index)); in inRange()
H A DHexagonMCDuplexInfo.cpp561 if (!isShiftedUInt<6, 0>(Value)) in subInstWouldBeExtended()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp798 return IsConstantImm && isShiftedUInt<1, 1>(Imm) && in isUImm2Lsb0()
808 return IsConstantImm && isShiftedUInt<5, 2>(Imm) && in isUImm7Lsb00()
818 return IsConstantImm && isShiftedUInt<6, 2>(Imm) && in isUImm8Lsb00()
828 return IsConstantImm && isShiftedUInt<5, 3>(Imm) && in isUImm8Lsb000()
840 return IsConstantImm && isShiftedUInt<6, 3>(Imm) && in isUImm9Lsb000()
850 return IsConstantImm && isShiftedUInt<8, 2>(Imm) && (Imm != 0) && in isUImm10Lsb00NonZero()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp218 return isShiftedUInt<23, 2>(static_cast<int32_t>(Value)); in isBrImm()
232 return Value != 0 && isShiftedUInt<16, 16>(Value); in isHiImm16()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h190 constexpr inline bool isShiftedUInt(uint64_t x) { in isShiftedUInt() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp247 return IsConstantImm && isShiftedUInt<num, shift>(Imm); in isUImm()
395 return isShiftedUInt<6, 0>(Imm) && uimm4 >= 0 && uimm4 <= 14; in isExtImm6()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td109 return isShiftedUInt<22, 10>(N->getZExtValue());
115 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue());
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp19525 return isShiftedUInt<7,2>(V); in isLegalT2AddressImmediate()
19528 return isShiftedUInt<7,1>(V); in isLegalT2AddressImmediate()
19538 return isShiftedUInt<8, 1>(V); in isLegalT2AddressImmediate()
19541 return isShiftedUInt<8, 2>(V); in isLegalT2AddressImmediate()
19586 return isShiftedUInt<8, 2>(V); in isLegalAddressImmediate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1403 isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm()); in isScaledUImm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10818 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal)) in LowerAsmOperandForConstraint()
10823 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) { in LowerAsmOperandForConstraint()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16755 if (isShiftedUInt<16, 16>(Value)) in LowerAsmOperandForConstraint()