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Searched refs:isShiftedInt (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td18 defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
21 defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
30 defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
33 defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
36 defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
54 defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
57 defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
60 defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
63 defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
66 defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>;
[all …]
H A DHexagonInstrInfo.cpp2916 return isShiftedInt<11,1>(Offset); in isValidOffset()
2920 return isShiftedInt<11,2>(Offset); in isValidOffset()
4083 isShiftedInt<6,3>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
H A DHexagonPatterns.td2674 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZicbo.td20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
27 return isShiftedInt<7, 5>(Imm);
H A DRISCVInstrInfoC.td145 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
153 return isShiftedInt<8, 1>(Imm);
195 [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
204 return isShiftedInt<6, 4>(Imm) && (Imm != 0);
210 ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
218 return isShiftedInt<11, 1>(Imm);
H A DRISCVInstrInfoZb.td211 return !isInt<13>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 2>(C);
220 return !isInt<14>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 3>(C);
H A DRISCVInstrInfo.cpp2005 Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0); in verifyInstruction()
2035 Ok = isShiftedInt<7, 5>(Imm); in verifyInstruction()
H A DRISCVInstrInfo.td255 return isShiftedInt<12, 1>(Imm);
306 return isShiftedInt<20, 1>(Imm);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYAsmBackend.cpp191 return !isShiftedInt<10, 1>(Offset); in fixupNeedsRelaxationAdvanced()
193 return !isShiftedInt<16, 1>(Offset); in fixupNeedsRelaxationAdvanced()
195 return !isShiftedInt<26, 1>(Offset); in fixupNeedsRelaxationAdvanced()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Dloongarch.h199 if (!isShiftedInt<26, 2>(Value)) in applyFixup()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp226 return IsConstantImm && isShiftedInt<N, S>(Imm) && in isSImm()
339 ? isShiftedInt<16, 2>(Imm) && IsValidKind in isSImm16lsl2()
433 ? isShiftedInt<21, 2>(Imm) && IsValidKind in isSImm21lsl2()
450 ? isShiftedInt<26, 2>(Imm) && IsValidKind in isSImm26Operand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h209 return isShiftedInt<N, S>(minConstant(MCI, Index)); in inSRange()
H A DHexagonMCDuplexInfo.cpp546 if (!isShiftedInt<7, 0>(Value)) in subInstWouldBeExtended()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1351 return !isShiftedInt<11, 1>( in lowerINTRINSIC_W_CHAIN()
1358 return !isShiftedInt<10, 2>( in lowerINTRINSIC_W_CHAIN()
1365 return !isShiftedInt<9, 3>( in lowerINTRINSIC_W_CHAIN()
1504 return (!isShiftedInt<8, 1>( in lowerINTRINSIC_VOID()
1511 return (!isShiftedInt<8, 1>( in lowerINTRINSIC_VOID()
1518 return (!isShiftedInt<8, 2>( in lowerINTRINSIC_VOID()
1525 return (!isShiftedInt<8, 2>( in lowerINTRINSIC_VOID()
1532 return (!isShiftedInt<8, 3>( in lowerINTRINSIC_VOID()
1539 return (!isShiftedInt<8, 3>( in lowerINTRINSIC_VOID()
4882 if (!isInt<12>(AM.BaseOffs) || !isShiftedInt<14, 2>(AM.BaseOffs)) in isLegalAddressingMode()
H A DLoongArchInstrInfo.td348 ImmLeaf<GRLenVT, [{return isShiftedInt<14,2>(Imm);}]> {
435 ImmLeaf<GRLenVT, [{return isShiftedInt<16, 16>(Imm);}]>;
440 return isShiftedInt<16, 16>(Imm - SignExtend64<12>(Imm));
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h166 constexpr inline bool isShiftedInt(int64_t x) { in isShiftedInt() function
/freebsd-14.2/contrib/llvm-project/lld/MachO/Arch/
H A DARM64.cpp298 return ldr.p2Size > 1 && isShiftedInt<19, 2>(ldr.offset); in isLiteralLdrEligible()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp511 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
889 return IsConstantImm && isShiftedInt<7, 5>(Imm) && in isSImm12Lsb00000()
901 return IsConstantImm && (Imm != 0) && isShiftedInt<6, 4>(Imm) && in isSImm10Lsb0000NonZero()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp265 return IsConstantImm && isShiftedInt<num, shift>(Imm); in isSImm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1358 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1362 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
1409 isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) in isScaledSImm()
1417 return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); in isScaledSImm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1577 isShiftedInt<7, 3>(NewOffset)) { in matchLDPSTPAddrMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td128 ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16759 if (isShiftedInt<16, 16>(Value)) in LowerAsmOperandForConstraint()