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Searched refs:isRegLoc (Results 1 – 25 of 32) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
223 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
229 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
283 if (Loc1.isRegLoc() && Loc2.isRegLoc()) in resultsCompatible()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp114 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
153 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
154 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
287 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
329 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
330 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
H A DARMFastISel.cpp1899 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1905 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1979 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1991 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2121 if (!VA.isRegLoc()) in SelectRet()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp324 if (VA.isRegLoc()) { in LowerCall()
416 if (VA.isRegLoc()) { in lowerCallResult()
521 if (VA.isRegLoc()) { in LowerCallArguments()
672 if (VA.isRegLoc()) in LowerReturn()
700 if (!VA.isRegLoc()) in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp719 assert(VA.isRegLoc() && NextVA.isRegLoc() && in Passv64i1ArgInRegs()
761 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1016 assert(VA.isRegLoc() && NextVA.isRegLoc() && in getv64i1Argument()
1716 if (VA.isRegLoc()) { in LowerFormalArguments()
1805 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) { in LowerFormalArguments()
2211 } else if (VA.isRegLoc()) { in LowerCall()
2322 if (VA.isRegLoc()) { in LowerCall()
2776 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2842 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2865 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
H A DX86FastISel.cpp1234 if (!VA.isRegLoc()) in X86SelectRet()
3434 if (VA.isRegLoc()) { in fastLowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp305 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpack64()
359 else if (VA.isRegLoc()) in LowerFormalArguments()
456 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
462 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
578 if (IsF64OnCSKY && VA.isRegLoc()) { in LowerCall()
611 if (VA.isRegLoc()) { in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1032 if (!ArgLoc.isRegLoc()) in parametersInCSRMatch()
1111 if (Loc1.isRegLoc() != Loc2.isRegLoc()) in resultsCompatible()
1114 if (Loc1.isRegLoc()) { in resultsCompatible()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp348 if (VA.isRegLoc()) { in LowerFormalArguments()
475 if (VA.isRegLoc()) in LowerCall()
562 if (!VA.isRegLoc()) in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp143 if (VAHi.isRegLoc()) in assignCustomValue()
264 if (VAHi.isRegLoc()) in assignCustomValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp283 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
366 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
464 if (VA.isRegLoc()) { in LowerFormalArguments_32()
643 if (VA.isRegLoc()) { in LowerFormalArguments_64()
980 if (VA.isRegLoc()) { in LowerCall_32()
984 if (NextVA.isRegLoc()) { in LowerCall_32()
1014 if (VA.isRegLoc()) { in LowerCall_32()
1115 assert(RVLocs[i].isRegLoc() && "Can only return in registers!"); in LowerCall_32()
1301 if (VA.isRegLoc()) { in LowerCall_64()
1342 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h122 bool isRegLoc() const { return std::holds_alternative<Register>(Data); } in isRegLoc() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp978 if (VA.isRegLoc()) { in LowerCallResult()
1071 if (VA.isRegLoc()) { in LowerCCCCallTo()
1207 if (VA.isRegLoc()) { in LowerCCCArguments()
1374 if (VA.isRegLoc()) in LowerReturn()
1402 if (!VA.isRegLoc()) in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp680 if (VA.isRegLoc()) { in LowerCall()
725 if (VA.isRegLoc()) in LowerCall()
945 if (VA.isRegLoc()) { in LowerFormalArguments()
1093 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1268 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1311 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
1335 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp456 if (VA.isRegLoc()) { in LowerCCCArguments()
562 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
692 if (VA.isRegLoc()) { in LowerCCCCallTo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp641 if (VA.isRegLoc()) { in LowerCCCArguments()
763 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
850 if (VA.isRegLoc()) { in LowerCCCCallTo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1398 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1506 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1746 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
H A DPPCISelLowering.cpp4176 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
5247 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
6028 if (VA.isRegLoc()) { in LowerCall_32SVR4()
7172 if (VA.isRegLoc()) { in LowerFormalArguments_AIX()
7223 assert(VA.isRegLoc() && "MemLocs should already be handled."); in LowerFormalArguments_AIX()
7265 for (; Offset != StackSize && ArgLocs[I].isRegLoc(); in LowerFormalArguments_AIX()
7287 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerFormalArguments_AIX()
7538 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerCall_AIX()
7559 assert(ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() && in LowerCall_AIX()
7605 assert(VA.isRegLoc() && VA.needsCustom() && CFlags.IsVarArg && in LowerCall_AIX()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1223 if (VA.isRegLoc() && !VA.needsCustom()) { in processCallArgs()
1714 if (!VA.isRegLoc()) in selectRet()
H A DMipsISelLowering.cpp3306 if (VA.isRegLoc()) { in LowerCall()
3362 if (VA.isRegLoc()) { in LowerCall()
3522 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3671 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
3842 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp388 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
465 if (VA.isRegLoc()) { in LowerFormalArguments()
723 if (VA.isRegLoc()) { in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp898 if (ArgLoc.isRegLoc()) in areCalleeOutgoingArgsTailCallable()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp520 if (VA.isRegLoc()) in LowerCall()
831 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8) in LowerFormalArguments()
834 bool InReg = VA.isRegLoc() && in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1408 if (VA.isRegLoc()) { in LowerFormalArguments()
1734 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp3889 if (VA.isRegLoc()) in LowerFormalArguments()
4193 if (VA.isRegLoc()) { in LowerCall()
4361 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()

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