| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 145 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad() local
150 if ((!isPre && Offs != 1) || (isPre && Offs != -1)) { in selectIndexedLoad()
154 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi; in selectIndexedLoad()
158 if ((!isPre && Offs != 2) || (isPre && Offs != -2)) { in selectIndexedLoad()
162 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi; in selectIndexedLoad()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 100 bool isPre() const { return getOperand(4).getImm() == 1; } in isPre() function
101 bool isPost() const { return !isPre(); } in isPost()
160 bool isPre() const { return getOperand(4).getImm() == 1; } in isPre() function
161 bool isPost() const { return !isPre(); } in isPost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1600 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1604 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1610 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1617 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1618 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1626 if (isPre && in tryARMIndexedLoad()
1630 } else if (!isPre && in tryARMIndexedLoad()
1710 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1749 bool isSExtLd, isPre; in tryMVEIndexedLoad() local
1768 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
[all …]
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| H A D | ARMInstrFormats.td | 783 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
790 let Inst{24} = isPre; // P bit
792 let Inst{21} = isPre; // W bit
796 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
799 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
814 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
817 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
833 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
872 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
879 let Inst{24} = isPre; // P bit
[all …]
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| H A D | ARMBaseInstrInfo.cpp | 188 bool isPre = false; in convertToThreeAddress() local
192 isPre = true; in convertToThreeAddress()
277 if (isPre) { in convertToThreeAddress()
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| /freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 611 bool isInc, bool isPre);
2552 bool isInc, bool isPre) { in EmitScalarPrePostIncDec() argument
2566 if (isPre) { in EmitScalarPrePostIncDec()
2594 return isPre ? Builder.CreateBinOp(op, old, amt) : old; in EmitScalarPrePostIncDec()
2844 return isPre ? value : input; in EmitScalarPrePostIncDec()
2855 return isPre ? value : input; in EmitScalarPrePostIncDec()
5199 bool isInc, bool isPre) { in EmitScalarPrePostIncDec() argument
5200 return ScalarExprEmitter(*this).EmitScalarPrePostIncDec(E, LV, isInc, isPre); in EmitScalarPrePostIncDec()
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| H A D | CGExprComplex.cpp | 196 bool isInc, bool isPre) { in VisitPrePostIncDec() argument
198 return CGF.EmitComplexPrePostIncDec(E, LV, isInc, isPre); in VisitPrePostIncDec()
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| H A D | CodeGenFunction.h | 3097 bool isInc, bool isPre);
3099 bool isInc, bool isPre);
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| H A D | CGExpr.cpp | 1213 bool isInc, bool isPre) { in EmitComplexPrePostIncDec() argument
1244 return isPre ? IncVal : InVal; in EmitComplexPrePostIncDec()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5621 bool IsPre = ExtLd.isPre(); in selectIndexedExtLoad()
5713 if (Ld.isPre()) { in selectIndexedLoad()
5757 if (I.isPre()) { in selectIndexedStore()
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