| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RDFRegisters.cpp | 143 assert(RR.isMask()); in getUnits()
264 assert(A.isMask()); in print()
280 if (RR.isMask()) in hasAliasOf()
293 if (RR.isMask()) { in hasCoverOf()
308 if (RR.isMask()) { in insert()
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| H A D | CodeGenPrepare.cpp | 6816 if (ActiveBits <= 1 || !DemandBits.isMask(ActiveBits) || in optimizeLoadExt()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 201 if (M.intersects(C) || !M.isMask(W)) in INITIALIZE_PASS_DEPENDENCY()
207 if (!M.getLoBits(U).isMask(W)) in INITIALIZE_PASS_DEPENDENCY()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | DemandedBits.cpp | 153 if (AOut.isMask()) { in determineLiveOperandBits()
161 if (AOut.isMask()) { in determineLiveOperandBits()
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| H A D | InstructionSimplify.cpp | 2463 if (C2->isMask() && // C2 == 0+1+ in simplifyOrInst()
2470 if (C1->isMask() && match(B, m_c_Add(m_Specific(A), m_Value(N)))) { in simplifyOrInst()
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| H A D | ScalarEvolution.cpp | 7861 if (CI->getValue().isMask(Z0TySize)) in createSCEV()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 51 static bool isMask(const TargetRegisterClass *RC, in isMask() function
60 if (isMask(RC, TRI)) in getDomain()
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| H A D | X86ISelLowering.cpp | 45895 NumElts <= CmpBits && CmpVal.isMask(NumElts); in combineSetCCMOVMSK()
47125 if (MaskVal.isMask()) { in combineShiftRightLogical()
48256 if (!X86::isConstantSplat(Op1, SplatVal, false) || !SplatVal.isMask()) in combineAndMaskToShift()
48447 !C1->getAPIntValue().isMask(SubVecVT.getVectorNumElements())) in combineScalarAndWithMaskSetcc()
49640 if (C2.isMask(VT.getScalarSizeInBits())) in detectUSatPattern()
49645 if (C1.isNonNegative() && C2.isMask(VT.getScalarSizeInBits())) in detectUSatPattern()
49650 if (C1.isNonNegative() && C2.isMask(VT.getScalarSizeInBits()) && in detectUSatPattern()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RDFRegisters.h | 100 constexpr bool isMask() const { return isMaskId(Reg); } in isMask() function
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 466 bool isMask(unsigned numBits) const { in isMask() function
479 bool isMask() const { in isMask() function
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | CorrelatedValuePropagation.cpp | 1121 if (!RHS || !RHS->getValue().isMask()) in processAnd()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 1304 if (NewNumElts >= VWidth && DemandedElts.isMask()) { in simplifyAMDGCNMemoryIntrinsicDemanded()
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| H A D | SIInstrInfo.cpp | 9687 const auto isMask = [&Mask, SrcSize](const MachineOperand *MO) -> bool { in optimizeCompareInstr() local
9697 if (isMask(SrcOp)) in optimizeCompareInstr()
9699 else if (isMask(&Def->getOperand(2))) in optimizeCompareInstr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 938 if (C2->isMask()) { in foldAddWithConstant()
2334 if (Op0C->isMask()) { in visitSub()
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| H A D | InstCombineAndOrXor.cpp | 2290 C->isMask(Width - ShiftC->getZExtValue())) in visitAnd()
2346 C->isMask(X->getType()->getScalarSizeInBits())) { in visitAnd()
2356 C->isMask(X->getType()->getScalarSizeInBits())) { in visitAnd()
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| H A D | InstCombineSelect.cpp | 638 if (!C1->isMask() || in foldSelectICmpAndZeroShl()
2824 if (!LowBitMaskCst->isMask()) in foldRoundUpIntegerWithPow2Alignment()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 589 bool isValue(const APInt &C) { return C.isMask(); } in isValue()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 753 if (!MaskVal.isMask()) in matchCombineLoadWithAndMask()
4860 if (!Mask.isMask()) in matchNarrowBinopFeedingAnd()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6415 if (!AndC->getAPIntValue().isMask()) in isAndLoadExtLoad()
6632 if (!Mask->getAPIntValue().isMask()) in BackwardsPropagateMask()
6995 if (Splat->getAPIntValue().isMask(ElementSize)) { in visitAND()
7203 if (N1C->getAPIntValue().isMask(ScalarWidth) && in visitAND()
7340 if (!C->getAPIntValue().isMask( in visitAND()
12592 ShiftOpc == ISD::SHL ? (~*AndCMask).isMask() : AndCMask->isMask(); in visitSETCC()
14237 if (Mask.isMask()) { in reduceLoadWidth()
14305 if (ShiftMask.isMask()) { in reduceLoadWidth()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17051 if (!V1.isMask(HalfSize) || V2 != (1ULL | 1ULL << HalfSize) || in performMulVectorCmpZeroCombine()
22080 if (!SubsAP.isMask()) in performSubsToAndsCombine()
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