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Searched refs:isAssignedRegDep (Results 1 – 12 of 12) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp149 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
164 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
H A DHexagonSubtarget.cpp560 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()
609 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()
625 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
H A DHexagonVLIWPacketizer.cpp1922 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in calcStall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp160 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()
189 if (Succ.isAssignedRegDep()) { in ScheduleNodeBottomUp()
480 if (Pred.isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
H A DScheduleDAGVLIW.cpp136 assert(!Succ.isAssignedRegDep() && in releaseSuccessors()
H A DScheduleDAGRRList.cpp560 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()
774 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { in ScheduleNodeBottomUp()
843 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ in UnscheduleNodeBottomUp()
889 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()
903 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()
1358 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) in DelayForLiveRegsBottomUp()
2869 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()
3045 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAG.cpp85 if (TRI && isAssignedRegDep()) in dump()
710 if (PredDep.isAssignedRegDep() && in WillCreateCycle()
H A DVLIWMachineScheduler.cpp711 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()
720 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
H A DMachinePipeliner.cpp3176 if (SI.isAssignedRegDep() && !SI.getSUnit()->isBoundaryNode()) in isValidSchedule()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h211 bool isAssignedRegDep() const { in isAssignedRegDep() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp1001 if (D.isAssignedRegDep()) { in computeSUnitReadyCycle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp6867 } else if (S.isAssignedRegDep()) { in tooMuchRegisterPressure()
6947 if (S.isAssignedRegDep()) { in tooMuchRegisterPressure()