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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKY.td73 "Support CSKY floate1 instructions">;
127 "Support CSKY dsp1e2 instructions">;
165 "Enable trust instructions">;
171 "Enable java instructions">;
189 "Enable doloop instructions">;
191 // Other features than instructions
208 "Enable vdsp-v2 instructions">;
270 "Support CSKY e1 instructions">;
277 "Support CSKY e2 instructions">;
283 "Support CSKY 2e3 instructions">;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPC.td67 "Enable floating-point instructions">;
85 "Enable SPE instructions",
151 "Enable VSX instructions",
167 "Enable Power8 direct move instructions",
274 def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",
307 "32Byte load and store instructions",
310 "Enable MMA instructions",
319 "Add privileged instructions">;
497 // The key column are the non-record-form instructions.
510 // The key column are the record-form instructions.
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H A DP10InstrResources.td20 // 2-way crack instructions
40 // 2-way crack instructions
61 // 2-way crack instructions
76 // 2-way crack instructions
249 // 2-way crack instructions
256 // 2-way crack instructions
1339 // Expand instructions
1346 // Expand instructions
1891 // Expand instructions
1907 // Expand instructions
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H A DPPCScheduleP9.td13 // The maximum number of instructions to be issued at the same time.
14 // While a value of 8 is technically correct since 8 instructions can be
15 // fetched from the instruction cache. However, only 6 instructions may be
21 // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
23 // of instructions are 4 or 5 cycles.
30 // A dispatch group is 6 instructions.
41 // Do not support SPE (Signal Processing Engine) or prefixed instructions on
43 // instructions introduced after ISA 3.0.
72 // Execution (EXEC) for most other instructions.
193 // receive new instructions each cycle.
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARM.td148 // True if the subtarget supports CLREX instructions.
200 // True if processor supports CRC instructions.
350 // True if VFP instructions are not pipelined.
397 /// True if codegen would avoid using instructions
426 // instructions.
464 // Generate calls via indirect call instructions.
592 // True if Thumb2 instructions are supported.
614 "v5TExp instructions",
715 "Support ARM v8-1M Mainline instructions",
744 "instructions">;
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H A DARMScheduleM55.td17 // Cortex-M4 are MVE instructions and the ability to dual issue thumb1
18 // instructions.
23 // The EPU pipelines now include both MVE and FP instructions. It has four
63 // instructions will become thumb1 instructions. We are quite optimistic, and
68 // Set IssueWidth to 2 to allow 2 instructions per cycle.
70 // instructions)
131 // DX instructions are ALU instructions that take a single cycle. The
175 // CX instructions take 2 (or more) cycles. Again T1 instructions may be dual
219 // Dual Issue instructions
310 // MVE instructions
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagon.td31 "Hexagon ZReg extension instructions">;
33 "true", "Hexagon HVX QFloating point instructions">;
36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
38 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
41 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
44 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
47 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
76 "Hexagon Audio extension instructions">;
82 "Use compound instructions">;
92 "Use memop instructions">;
[all …]
H A DHexagonInstrFormats.td9 // Addressing modes for load/store instructions
64 // instructions to not match without killing the whole decode process. It is
75 // Solo instructions, i.e., those that cannot be in a packet with others.
78 // Packed only with A or X-type instructions.
81 // Restricts slot 1 to ALU-only instructions.
85 // Predicated instructions.
135 // Addressing mode for load/store instructions.
139 // Memory access size for mem access instructions (load/store)
188 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
291 // instructions to not match without killing the whole decode process. It is
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td309 "Additional instructions for CI+"
381 "Has i16/f16 instructions"
399 "Has VOP3P packed instructions"
405 "Has v_movrel*_b32 instructions"
532 "Support image instructions"
640 "Has mAI instructions"
646 "Has fp8 and bf8 instructions"
665 "ds_pk_add_rtn_f16 instructions"
797 "Has ds_*_src2 instructions"
933 // instructions.
[all …]
H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
34 // F16 or F32 transcendental instructions (these are quarter rate)
36 // Other quarter rate VALU instructions
51 // instructions
54 // Half rate 64-bit instructions.
60 // mAI multipass instructions.
68 // Scalar float instructions
71 // F16 or F32 pseudo scalar transcendental instructions
74 // FIXME: Should there be a class for instructions which are VALU
75 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td16 // Check the shift in arithmetic and logic instructions.
32 // Identify arithmetic instructions without or with limited extension or shift.
60 // Identify logic instructions with limited shift.
76 // Identify more logic instructions with limited shift.
111 // Identify FP instructions.
114 // Identify 128-bit NEON instructions.
117 // Identify instructions that reset a register efficiently.
135 // Identify cheap arithmetic and logic immediate instructions.
H A DAArch64SchedPredicates.td16 // Check the extension type in arithmetic instructions.
28 // Check for shifting in extended arithmetic instructions.
34 // Check for shifting in arithmetic and logic instructions.
93 // Identify arithmetic instructions with extend.
99 // Identify arithmetic immediate instructions.
103 // Identify arithmetic instructions with shift.
107 // Identify arithmetic instructions without shift.
111 // Identify logic immediate instructions.
116 // Identify logic instructions with shift.
124 // Identify logic instructions without shift.
[all …]
H A DAArch64.td62 "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">;
78 "Enable out of line atomics to support LSE instructions">;
110 "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>;
134 "Enable FP8 instructions (FEAT_FP8)">;
237 "Use Exynos specific handling of cheap instructions">;
521 "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
524 "Enable fp8 multiply-add instructions (FEAT_FP8FMA)">;
530 "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">;
536 "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">;
541 "Enable Lookup Table instructions (FEAT_LUT)">;
[all …]
H A DAArch64SchedExynosM3.td194 // Branch instructions.
204 // Move instructions.
225 // Load instructions.
231 // Store instructions.
237 // FP data instructions.
493 // Branch instructions
508 // Move instructions.
517 // Load instructions.
530 // Store instructions.
607 // ASIMD instructions.
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86.td70 "Enable SSE instructions">;
72 "Enable SSE2 instructions",
424 "instructions into a POP+LFENCE+JMP sequence.">;
659 // rotate instructions.
666 // instructions) with conditional branches.
688 "Prefer no gather instructions">;
691 "Prefer no scatter instructions">;
695 "Prefer 128-bit AVX instructions">;
699 "Prefer 256-bit AVX instructions">;
720 "normal vector instructions with shuffles">;
[all …]
H A DX86InstrInfo.td9 // This file describes the X86 properties of the instructions which are needed
75 // Key Locker instructions
78 // AMX instructions
81 // RAO-INT instructions
84 // System instructions.
H A DX86InstrTDX.td9 // This file describes the instructions that make up the Intel TDX instruction
15 // TDX instructions
17 // 64-bit only instructions
29 // common instructions
H A DX86InstrUtils.td120 // PL - Helper for promoted legacy instructions
479 // SI - SSE 1 & 2 scalar instructions
527 // PI - SSE 1 & 2 packed instructions
567 // SSI - SSE1 instructions with XS prefix.
568 // PSI - SSE1 instructions with PS prefix.
598 // SDI - SSE2 instructions with XD prefix.
600 // S2SI - SSE2 instructions with XS prefix.
663 // S3SI - SSE3 instructions with XS prefix.
664 // S3DI - SSE3 instructions with XD prefix.
682 // SS38I - SSSE3 instructions with T8 prefix.
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td27 // When there are multiple instructions that map to the same encoding (in
32 // Normal instructions. Default instantiation of a WebAssemblyInst.
48 // instructions are used for ISel and all MI passes. The stack versions of the
49 // instructions do not have register operands (they implicitly operate on the
50 // stack), and local.gets and local.sets are explicit. The register instructions
51 // are converted to their corresponding stack instructions before lowering to
54 // there is always an equivalent pair of instructions.
64 // For instructions that have no register ops, so both sets are the same.
/freebsd-14.2/usr.bin/bc/
H A Dbc.y98 static struct tree *instructions = NULL; variable
774 free(instructions);
777 instructions = p;
788 instructions[current].u.cstr = str; in cs()
799 if (instructions[current].u.astr == NULL) in as()
814 instructions[current++].index = arg; in node()
819 instructions[current++].index = arg; in node()
832 if (instructions[i].index >= 0) { in emit()
834 instructions[i].index != i) { in emit()
839 fputs(instructions[i].u.cstr, stdout); in emit()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td17 // Class for registers that are the result of OpTypeXXX instructions
35 // A few instructions like OpName can take ids from both type and non-type
36 // instructions, so we need a super-class to allow for both to count as valid
37 // arguments for these instructions.
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsPPC.def67 TARGET_BUILTIN(__builtin_ppc_icbt, "vv*", "", "isa-v207-instructions")
95 TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*", "", "isa-v207-instructions")
114 // fence builtin prevents all instructions moved across it
140 "isa-v30-instructions")
159 TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
520 "isa-v207-instructions")
522 "isa-v207-instructions")
524 "isa-v207-instructions")
526 "isa-v207-instructions")
940 TARGET_BUILTIN(__builtin_darn, "LLi", "", "isa-v30-instructions")
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZvfbf.td1 //===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===//
9 // This file describes the RISC-V instructions from the standard 'Zvfbfmin'
10 // extension, providing vector conversion instructions for BFloat16.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td42 // A class for pseudo instructions.
43 // Pseudo instructions are not real AVR instructions. The DAG stores
44 // pseudo instructions which are replaced by real AVR instructions by
198 // Special format for the LPM/ELPM instructions
260 // Special encoding for the FMUL family of instructions.
285 // Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
411 // Conditional Branching instructions: <|1111|0fkk|kkkk|ksss|>
429 // Special, opcode only instructions: <|opcode|>
438 // Branching instructions with immediate12: <|110f|kkkk|kkkk|kkkk|>
494 // Special format for the LDS/STS instructions on AVRTiny.
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMSA.txt7 (semantically equivalent) instructions to be used in place of the requested
14 example, two instructions might be equally valid for some given IR and one is
31 instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
32 and pck* instructions, this is matched from MipsISD::VSHF instead of
68 In future, the compiler may choose between these three instructions
71 between the instructions and the vselect node in one place:

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