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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def112 /// BUNDLE - This instruction represents an instruction bundle. Instructions
135 /// Patchable call instruction - this instruction represents a call to a
249 // Generic multiply instruction.
252 // Generic signed division instruction.
258 // Generic signed remainder instruction.
264 // Generic signed divrem instruction.
267 // Generic unsigned divrem instruction.
270 /// Generic bitwise and instruction.
273 /// Generic bitwise or instruction.
282 /// Generic PHI instruction with types.
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DLeonFeatures.td17 //support to casa instruction; for leon3 subtarget only
31 //support to casa instruction; for leon3 subtarget only
36 "Enable CASA instruction for LEON3 and LEON4 processors"
43 …m fix: Insert a NOP instruction after every single-cycle load instruction when the next instructio…
/freebsd-14.2/contrib/xz/src/liblzma/simple/
H A Dia64.c41 uint64_t instruction = 0; in ia64_code() local
44 instruction += (uint64_t)( in ia64_code()
48 uint64_t inst_norm = instruction >> bit_res; in ia64_code()
73 instruction &= (1U << bit_res) - 1; in ia64_code()
74 instruction |= (inst_norm << bit_res); in ia64_code()
78 instruction in ia64_code()
/freebsd-14.2/contrib/llvm-project/lldb/include/lldb/Core/
H A DEmulateInstruction.h331 void Dump(Stream &s, EmulateInstruction *instruction) const;
334 typedef size_t (*ReadMemoryCallback)(EmulateInstruction *instruction,
339 typedef size_t (*WriteMemoryCallback)(EmulateInstruction *instruction,
344 typedef bool (*ReadRegisterCallback)(EmulateInstruction *instruction,
349 typedef bool (*WriteRegisterCallback)(EmulateInstruction *instruction,
442 static size_t ReadMemoryFrame(EmulateInstruction *instruction, void *baton,
446 static size_t WriteMemoryFrame(EmulateInstruction *instruction, void *baton,
450 static bool ReadRegisterFrame(EmulateInstruction *instruction, void *baton,
454 static bool WriteRegisterFrame(EmulateInstruction *instruction, void *baton,
459 static size_t ReadMemoryDefault(EmulateInstruction *instruction, void *baton,
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/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/UnwindAssembly/InstEmulation/
H A DUnwindAssemblyInstEmulation.h78 ReadMemory(lldb_private::EmulateInstruction *instruction, void *baton,
83 WriteMemory(lldb_private::EmulateInstruction *instruction, void *baton,
87 static bool ReadRegister(lldb_private::EmulateInstruction *instruction,
93 WriteRegister(lldb_private::EmulateInstruction *instruction, void *baton,
105 size_t WriteMemory(lldb_private::EmulateInstruction *instruction,
109 bool ReadRegister(lldb_private::EmulateInstruction *instruction,
113 bool WriteRegister(lldb_private::EmulateInstruction *instruction,
H A DUnwindAssemblyInstEmulation.cpp379 EmulateInstruction *instruction, void *baton, in ReadMemory() argument
390 context.Dump(strm, instruction); in ReadMemory()
398 EmulateInstruction *instruction, void *baton, in WriteMemory() argument
403 ->WriteMemory(instruction, context, addr, dst, dst_len); in WriteMemory()
411 instruction->GetArchitecture().GetByteOrder(), in WriteMemory()
412 instruction->GetArchitecture().GetAddressByteSize()); in WriteMemory()
423 context.Dump(strm, instruction); in WriteMemory()
487 ->ReadRegister(instruction, reg_info, reg_value); in ReadRegister()
510 EmulateInstruction *instruction, void *baton, in WriteRegister() argument
515 ->WriteRegister(instruction, context, reg_info, reg_value); in WriteRegister()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td10 // which should be implemented by each target that uses instruction
12 // tables for each instruction class. They are most appropriate for
22 // during scheduling and has an affect instruction order based on availability
43 // the execution of an instruction. Cycles represents the number of
68 // instruction stages.
72 // Instruction itinerary classes - These values represent 'named' instruction
76 // instruction information.
83 // instruction itinerary class (name) to its itinerary data.
87 // instruction can decode into variable number of micro-ops and it must be
93 // instruction issue the values which correspond to specific operand indices
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H A DTarget.td610 // instruction.
611 bit isReturn = false; // Is this instruction a return instruction?
612 bit isBranch = false; // Is this instruction a branch instruction?
618 bit isBitcast = false; // Is this instruction a bitcast instruction?
619 bit isSelect = false; // Is this instruction a select instruction?
621 bit isCall = false; // Is this instruction a call instruction?
622 bit isAdd = false; // Is this instruction an add instruction?
623 bit isTrap = false; // Is this instruction a trap instruction?
650 bit isPseudo = false; // Is this instruction a pseudo-instruction?
653 bit isMeta = false; // Is this instruction a meta-instruction?
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/freebsd-14.2/contrib/llvm-project/lld/MachO/Arch/
H A DARM64Common.cpp99 uint32_t instruction = read32le(loc); in relaxGotLoad() local
103 if ((instruction & 0xbfc00000) != 0xb9400000) in relaxGotLoad()
105 assert(((instruction >> 10) & 0xfff) == 0 && in relaxGotLoad()
109 instruction = ((instruction & 0x001fffff) | 0x91000000); in relaxGotLoad()
110 write32le(loc, instruction); in relaxGotLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td33 // This class does not depend on the instruction size
69 // For 32 bit extended instruction forms.
377 // Format i8_SVRS instruction class in Mips :
404 // Format JAL instruction class in Mips16 :
427 // Format EXT-I instruction class in Mips16 :
449 // Format ASMACRO instruction class in Mips16 :
478 // Format EXT-RI instruction class in Mips16 :
502 // Format EXT-RRI instruction class in Mips16 :
527 // Format EXT-RRI-A instruction class in Mips16 :
553 // Format EXT-SHIFT instruction class in Mips16 :
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td9 // This file describes the RISC-V C extension instruction formats.
37 // The immediate value encoding differs for each instruction, so each subclass
39 // The bits Inst{6-2} must be set for each instruction.
52 // The immediate value encoding differs for each instruction, so each subclass
54 // The bits Inst{12-7} must be set for each instruction.
80 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
95 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
162 // The bits Inst{6-5} must be set for each instruction.
177 // The bits Inst{5} must be set for each instruction.
193 // The bits Inst{6-5} must be set for each instruction.
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H A DRISCVInstrInfoVPseudos.td18 /// specific instruction, but the common dimensions are:
5501 : VPatBinaryV_VM_TAIL<intrinsic, instruction>,
5502 VPatBinaryV_XM_TAIL<intrinsic, instruction>,
5503 VPatBinaryV_IM_TAIL<intrinsic, instruction>;
5511 : VPatBinaryV_V<intrinsic, instruction>,
5512 VPatBinaryV_X<intrinsic, instruction>,
5513 VPatBinaryV_I<intrinsic, instruction>;
5516 : VPatBinaryV_VM_TAIL<intrinsic, instruction>,
5517 VPatBinaryV_XM_TAIL<intrinsic, instruction>;
5524 : VPatBinaryV_V<intrinsic, instruction>,
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H A DRISCVInstrInfoZvk.td87 // op vd, vs2 (use vs1 as instruction encoding)
782 instruction#"_"#kind#"_"#vti.LMul.MX),
795 instruction#"_VI_"#vti.LMul.MX));
826 : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
827 VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
832 : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
833 VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
834 VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
865 : VPatBinaryW_VV<intrinsic, instruction, vtilist>,
866 VPatBinaryW_VX_VWSLL<intrinsic, instruction, vtilist>,
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/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulationStateARM.h41 ReadPseudoMemory(lldb_private::EmulateInstruction *instruction, void *baton,
46 WritePseudoMemory(lldb_private::EmulateInstruction *instruction, void *baton,
50 static bool ReadPseudoRegister(lldb_private::EmulateInstruction *instruction,
56 WritePseudoRegister(lldb_private::EmulateInstruction *instruction,
/freebsd-14.2/contrib/llvm-project/lldb/source/Core/
H A DEmulateInstruction.cpp257 size_t EmulateInstruction::ReadMemoryFrame(EmulateInstruction *instruction, in ReadMemoryFrame() argument
274 size_t EmulateInstruction::WriteMemoryFrame(EmulateInstruction *instruction, in WriteMemoryFrame() argument
292 bool EmulateInstruction::ReadRegisterFrame(EmulateInstruction *instruction, in ReadRegisterFrame() argument
303 bool EmulateInstruction::WriteRegisterFrame(EmulateInstruction *instruction, in WriteRegisterFrame() argument
314 size_t EmulateInstruction::ReadMemoryDefault(EmulateInstruction *instruction, in ReadMemoryDefault() argument
323 context.Dump(strm, instruction); in ReadMemoryDefault()
329 size_t EmulateInstruction::WriteMemoryDefault(EmulateInstruction *instruction, in WriteMemoryDefault() argument
338 context.Dump(strm, instruction); in WriteMemoryDefault()
343 bool EmulateInstruction::ReadRegisterDefault(EmulateInstruction *instruction, in ReadRegisterDefault() argument
359 bool EmulateInstruction::WriteRegisterDefault(EmulateInstruction *instruction, in WriteRegisterDefault() argument
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DTarget.td10 // SelectionDAG instruction selection patterns (specified in
11 // TargetSelectionDAG.td) when generating GlobalISel instruction selectors.
53 // renders directly to the result instruction without an intermediate node.
58 // The function renders the operand(s) of the matched instruction to
59 // the specified instruction. It should be of the form:
66 // where there is no corresponding instruction to match.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td20 // SALU instruction formats.
27 // VALU instruction formats.
38 // Memory instruction formats.
49 // Pseudo instruction formats.
53 // LDSDIR instruction format.
56 // VINTERP instruction format.
64 // Whether WQM _must_ be enabled for this instruction.
67 // Whether WQM _must_ be disabled for this instruction.
82 // instruction size.
93 // Is it possible for this instruction to be atomic?
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrFormats.td41 // except for the `AND' instruction (`AAA' = 100), for which the other
45 // `F' determines whether the instruction modifies (1) or does not
85 // The all-0s word is the instruction `R0 <- R0 + 0', which is a no-op.
117 // `DDDI' is as described for the BR instruction.
119 // `F' determines whether the instruction modifies (1) or does not
143 // the select instruction.
183 // following instruction reads Rd, that instruction will be delayed by 1
193 // The constant is sign-extended for this instruction.
231 // The RRM instruction is identical to the RM (*note RM::.) instruction
296 // The BR instruction is an absolute branch.
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td14 // Vector instruction type enum
44 // with 0 meaning the operation is not a surface instruction. For example,
45 // if IsSuld == 2, then the instruction is a suld instruction with vector size
/freebsd-14.2/crypto/openssl/doc/man3/
H A DOPENSSL_s390xcap.pod13 libcrypto supports z/Architecture instruction set extensions. These
15 When libcrypto is initialized, the bits returned by the STFLE instruction
36 implements the corresponding instruction set extension. Possible values
42 The name of an instruction followed by two 64-bit masks. The part of the
43 environment variable's mask corresponding to the specified instruction is
52 instruction is set to the specified 192-bit mask.
59 The following is a list of significant bits for each instruction. Colon
174 Disables all instruction set extensions which the z196 processor does not implement:
H A DOPENSSL_ia32cap.pod13 OpenSSL supports a range of x86[_64] instruction set extensions. These
15 by processor in EDX:ECX register pair after executing CPUID instruction
26 =item bit #19 denoting availability of CLFLUSH instruction;
43 =item bit #33 denoting availability of PCLMULQDQ instruction;
49 =item bit #54 denoting availability of MOVBE instruction;
51 =item bit #57 denoting AES-NI instruction set extension;
60 =item bit #62 denoting availability of RDRAND instruction;
102 =item bit #64+18 denoting availability of RDSEED instruction;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td75 // Identify whether an instruction is NEON or floating point
81 // Identify whether an instruction is the 16-bit NEON form based on its result.
144 // Identify whether an instruction is an ASIMD
173 // Identify whether an instruction is an ASIMD
194 // Identify whether an instruction is an ASIMD load
199 // Identify whether an instruction is a load
215 // Identify whether an instruction is a store
227 // Identify whether an instruction is a load or
281 // Identify an instruction that effectively transfers a register to another.
310 // Identify an instruction that effectively resets a GP register to zero.
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFormats.td13 // Format specifies the encoding used by the instruction. This is part of the
14 // ad-hoc solution used to emit machine instruction encodings by our machine
81 // ImmType - This specifies the immediate type used by an instruction. This is
148 // decode to this instruction. e.g. ANDSS/ANDSD don't
195 // Force the instruction to use REX2/VEX/EVEX encoding.
218 // If this is a pseudo instruction, mark it isCodeGenOnly.
230 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
233 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
237 Encoding OpEnc = EncNormal; // Encoding used by this instruction
244 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
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/freebsd-14.2/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m421 dnl instruction sets.
29 dnl although the instruction set of 'mips' is a large subset of the
30 dnl instruction set of 'mipsn32'.
33 dnl the instruction sets of 'mipsn32' and 'mips64' are the same.
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
103 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td10 /// WebAssembly instruction format definitions.
15 // We instantiate 2 of these for every actual instruction (register based
42 // Generates both register and stack based versions of one actual instruction.
44 // based version of this instruction, as well as the corresponding asmstr.
53 // Every instruction should want to be based on this multi-class to guarantee

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