| /freebsd-14.2/sys/riscv/riscv/ |
| H A D | db_disasm.c | 354 int imm; in oprint() local 382 if (imm & (1 << 8)) in oprint() 390 if (imm & (1 << 8)) in oprint() 401 if (imm & (1 << 8)) in oprint() 408 if (imm & (1 << 8)) in oprint() 415 if (imm & (1 << 5)) in oprint() 422 if (imm & (1 << 5)) in oprint() 481 if (imm & (1 << 12)) in oprint() 499 if (imm & (1 << 11)) in oprint() 506 if (imm & (1 << 11)) in oprint() [all …]
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| /freebsd-14.2/sys/cddl/dev/kinst/riscv/ |
| H A D | kinst_isa.c | 72 uint64_t imm; in kinst_emulate() local 87 imm = 0; in kinst_emulate() 96 frame->tf_sepc += imm; in kinst_emulate() 108 imm = 0; in kinst_emulate() 119 frame->tf_sepc += imm; in kinst_emulate() 125 frame->tf_sepc += imm; in kinst_emulate() 131 frame->tf_sepc += imm; in kinst_emulate() 159 imm | 0xffffffff80000000 : imm); in kinst_emulate() 180 imm = 0; in kinst_emulate() 191 frame->tf_sepc += imm; in kinst_emulate() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrCDE.td | 118 bits<13> imm; 124 let Inst{7} = imm{6}; 134 bits<9> imm; 142 let Inst{7} = imm{6}; 152 bits<6> imm; 279 bits<12> imm; 300 bits<11> imm; 335 bits<7> imm; 361 bits<6> imm; 402 bits<4> imm; [all …]
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| H A D | ARMInstrThumb2.td | 446 bits<12> imm; 460 bits<12> imm; 472 bits<12> imm; 556 bits<12> imm; 570 bits<12> imm; 584 bits<5> imm; 597 bits<5> imm; 1086 // 5-bit imm 4143 bits<8> imm; 4281 bits<8> imm; [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoC.td | 276 let Inst{2} = imm{4}; 314 let Inst{6} = imm{2}; 321 bits<8> imm; 328 bits<7> imm; 338 bits<7> imm; 347 bits<8> imm; 355 bits<8> imm; 362 bits<7> imm; 372 bits<7> imm; 381 bits<8> imm; [all …]
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| H A D | RISCVInstrInfoZc.td | 83 (ins GPRCMem:$rs1, uimm2:$imm), 84 OpcodeStr, "$rd, ${imm}(${rs1})"> { 85 bits<2> imm; 87 let Inst{6-5} = imm{0,1}; 94 OpcodeStr, "$rd, ${imm}(${rs1})"> { 95 bits<2> imm; 97 let Inst{5} = imm{1}; 105 bits<2> imm; 107 let Inst{6-5} = imm{0,1}; 115 bits<2> imm; [all …]
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| H A D | RISCVGISel.td | 33 def ImmPlus1 : SDNodeXForm<imm, [{ 86 def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)), 87 (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>; 90 def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)), 91 (ADDIW GPR:$rs1, (i64 (NegImm $imm)))>; 126 (ImmPlus1 simm12Minus1NonzeroNonNeg1:$imm)), 1)>; 133 def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12:$imm))), 134 (XORI (SLTIU GPR:$rs1, simm12:$imm), 1)>; 137 def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12:$imm))), 138 (XORI (SLTI GPR:$rs1, simm12:$imm), 1)>; [all …]
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| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_cde.td | 68 cgArgs, (? $imm))>; 80 (? $imm)):$pair, 86 defm cx1 : CDE_CX_m<(args imm_13b:$imm), (args), (?)>; 114 defm vcx3: CDE_VCXFP_m<(args imm_3b:$imm), 124 (CDEIRInt<"vcx1q"> $cp, $imm)>; 159 $imm), 178 ["cp", "acc", "n", "imm"], 182 ["cp", "n", "m", "imm"], 185 ["cp", "n", "m", "imm"], 188 ["cp", "acc", "n", "m", "imm"], [all …]
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| /freebsd-14.2/sys/cddl/dev/kinst/aarch64/ |
| H A D | kinst_isa.c | 25 uint64_t imm; in kinst_emulate() local 32 imm = (instr >> 29) & 0x3; in kinst_emulate() 37 imm |= 0xfffffffffff00000; in kinst_emulate() 41 imm <<= 12; in kinst_emulate() 43 imm |= 0xffffffff00000000; in kinst_emulate() 49 imm = instr & 0x03ffffff; in kinst_emulate() 51 imm |= 0xfffffffffe000000; in kinst_emulate() 52 frame->tf_elr += imm << 2; in kinst_emulate() 57 imm |= 0xfffffffffffc0000; in kinst_emulate() 97 imm = instr & 0x03ffffff; in kinst_emulate() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrAliases.td | 93 // b<cond> $imm 97 // b<cond>,a $imm 196 // t<cond> %icc, imm => t<cond> %icc, G0 + imm 204 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm 213 // t<cond> imm => t<cond> G0 + imm 217 // t<cond> rs1 + imm => t<cond> rs1 + imm 234 // fb<cond> $imm 238 // fb<cond>,a $imm 287 // cb<cond> $imm 563 // or imm, reg, rd -> or reg, imm, rd [all …]
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| H A D | SparcInstr64Bit.td | 69 def as_i32imm : SDNodeXForm<imm, [{ 83 def nimm33 : PatLeaf<(imm), [{ 88 def HIX22 : SDNodeXForm<imm, [{ 93 def LOX10 : SDNodeXForm<imm, [{ 127 def HH22 : SDNodeXForm<imm, [{ 132 def HM10 : SDNodeXForm<imm, [{ 136 def : Pat<(i64 imm:$val), 434 (MOVXCCrr $t, $f, imm:$cond)>; 439 (MOVICCrr $t, $f, imm:$cond)>; 444 (MOVFCCrr $t, $f, imm:$cond)>; [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 286 "call\t$imm", [(MSP430call imm:$imm)]>; 342 [(set GR8:$rd, imm:$imm)]>; 346 [(set GR16:$rd, imm:$imm)]>; 415 [(store (i8 imm:$imm), addr:$dst)]>; 419 [(store (i16 imm:$imm), addr:$dst)]>; 491 [(set GR8:$rd, (node GR8:$src2, imm:$imm)), 495 [(set GR16:$rd, (node GR16:$src2, imm:$imm)), 775 (i8 imm:$imm)), (implicit SR)]>; 780 (i16 imm:$imm)), (implicit SR)]>; 861 [(MSP430cmp (and_su GR8:$rd, imm:$imm), 0), [all …]
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| H A D | MSP430InstrFormats.td | 77 bits<16> imm; 88 bits<6> imm; 133 bits<16> imm; 147 bits<6> imm; 204 bits<16> imm; 215 bits<6> imm; 260 bits<16> imm; 274 bits<6> imm; 351 bits<16> imm; 361 bits<6> imm; [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.td | 210 bits<32> imm; 242 bits<32> imm; 277 bits<32> imm; 364 [(set GPR:$dst, (i64 imm:$imm))]> { 367 bits<64> imm; 444 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> { 447 bits<64> imm; 491 bits<32> imm; 738 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>; 1007 bits<32> imm; [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAsmAlias.td | 287 def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 289 def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 291 def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 598 def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 599 def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 600 def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 601 def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 602 def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 603 def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 604 def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 133 (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm)>; 135 (outs mGPR:$rz), (ins mGPR:$rx, uimm5_1:$imm)>; 137 (outs mGPR:$rz), (ins mGPR:$rx, uimm5_2:$imm)>; 139 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5:$imm)>; 141 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5_1:$imm)>; 143 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5_2:$imm)>; 564 def : Pat<(i32 imm:$imm), 565 (OR16 (MOVI16 (uimm8SRL_0 imm:$imm)), 566 (OR16 (LSLI16 (MOVI16 (uimm8SRL_8 imm:$imm)), 8), 567 (OR16 (LSLI16 (MOVI16 (uimm8SRL_16 imm:$imm)), 16), [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.td | 64 def LO16 : SDNodeXForm<imm, [{ 76 def NEG : SDNodeXForm<imm, [{ 336 def : Pat<(i32 i32lo16and:$imm), (AND_I_LO (i32 R1), i32lo16and:$imm)>; 337 def : Pat<(i32 i32hi16and:$imm), (AND_I_HI (i32 R1), i32hi16and:$imm)>; 432 def : Pat<(srl GPR:$Rs1, immShift:$imm), (SL_I GPR:$Rs1, (NEG $imm))>; 433 def : Pat<(sra GPR:$Rs1, immShift:$imm), (SA_I GPR:$Rs1, (NEG $imm))>; 585 bits<21> imm; 587 let msb = imm{20-16}; 588 let lsb = imm{15-0}; 832 def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>; [all …]
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| /freebsd-14.2/contrib/llvm-project/clang/lib/Headers/ |
| H A D | f16cintrin.h | 68 #define _cvtss_sh(a, imm) __extension__ ({ \ argument 70 (imm)))[0]); }) 95 #define _mm_cvtps_ph(a, imm) \ argument 96 ((__m128i)__builtin_ia32_vcvtps2ph((__v4sf)(__m128)(a), (imm))) 138 #define _mm256_cvtps_ph(a, imm) \ argument 139 ((__m128i)__builtin_ia32_vcvtps2ph256((__v8sf)(__m256)(a), (imm)))
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| H A D | avx512dqintrin.h | 1222 #define _mm512_extractf32x8_ps(A, imm) \ argument 1237 #define _mm512_extractf64x2_pd(A, imm) \ argument 1255 #define _mm512_extracti32x8_epi32(A, imm) \ argument 1288 #define _mm512_insertf32x8(A, B, imm) \ argument 1302 #define _mm512_insertf64x2(A, B, imm) \ argument 1316 #define _mm512_inserti32x8(A, B, imm) \ argument 1330 #define _mm512_inserti64x2(A, B, imm) \ argument 1348 #define _mm512_fpclass_ps_mask(A, imm) \ argument 1356 #define _mm512_fpclass_pd_mask(A, imm) \ argument 1360 #define _mm_fpclass_sd_mask(A, imm) \ argument [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchLASXInstrInfo.td | 1329 (XVORI_B LASX256:$xj, uimm8:$imm)>; 1803 // Pat<(Intrinsic timm:$imm) 1804 // (LAInst timm:$imm)>; 1806 (XVLDI (to_valid_timm timm:$imm))>; 1812 // Pat<(Intrinsic vty:$xj, timm:$imm) 1813 // (LAInst vty:$xj, timm:$imm)>; 1841 // (LAInst vty:$xd, vty:$xj, timm:$imm)>; 1849 (to_valid_timm timm:$imm))>; 1857 (to_valid_timm timm:$imm))>; 1865 (to_valid_timm timm:$imm))>; [all …]
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| H A D | LoongArchLSXInstrInfo.td | 1426 (VANDI_B LSX128:$vj, uimm8:$imm)>; 1429 (VORI_B LSX128:$vj, uimm8:$imm)>; 1433 (VXORI_B LSX128:$vj, uimm8:$imm)>; 1900 // Pat<(Intrinsic timm:$imm) 1901 // (LAInst timm:$imm)>; 1909 // Pat<(Intrinsic vty:$vj, timm:$imm) 1910 // (LAInst vty:$vj, timm:$imm)>; 1946 (to_valid_timm timm:$imm))>; 1954 (to_valid_timm timm:$imm))>; 1962 (to_valid_timm timm:$imm))>; [all …]
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| /freebsd-14.2/sys/arm64/arm64/ |
| H A D | disassem.c | 547 imm <<= 2; in disasm() 601 if (imm != 0) in disasm() 604 if (imm != 0 || shift != 0) in disasm() 605 di->di_printf(", #0x%x", imm); in disasm() 639 imm = imm << ((insn >> ARM_INSN_SIZE_OFFSET) & in disasm() 663 if (imm != 0) in disasm() 664 di->di_printf(", #%d", imm); in disasm() 668 if (imm != 0) in disasm() 669 di->di_printf(", #%d", imm); in disasm() 724 di->di_printf("0x%lx", loc + imm); in disasm() [all …]
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| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVCInstructions.h | 165 if ((imm & 0x20) == 0) in DecodeC_LI() 166 return ADDI{rd, Rs{0}, uint32_t(imm)}; in DecodeC_LI() 187 uint32_t imm = in DecodeC_LUI_ADDI16SP() local 189 if ((imm & 0x20000) == 0) in DecodeC_LUI_ADDI16SP() 190 return LUI{rd, imm}; in DecodeC_LUI_ADDI16SP() 199 if ((imm & 0x20) == 0) in DecodeC_ADDI() 200 return ADDI{rd, rd, uint32_t(imm)}; in DecodeC_ADDI() 209 if ((imm & 0x20) == 0) in DecodeC_ADDIW() 210 return ADDIW{rd, rd, uint32_t(imm)}; in DecodeC_ADDIW() 255 if ((imm & 0x20) == 0) in DecodeC_ANDI() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SMEInstrFormats.td | 220 bit imm; 1198 bits<8> imm; 1830 bits<2> imm; 1866 bits<2> imm; 1956 bits<2> imm; 2029 bits<2> imm; 2073 bits<2> imm; 2802 bit imm; 2861 bit imm; 2923 bits<2> imm; [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips64InstrInfo.td | 23 def immSExt10_64 : PatLeaf<(i64 imm), 26 def immZExt16_64 : PatLeaf<(i64 imm), 32 def Log2LO : SDNodeXForm<imm, [{ 37 def Log2HI : SDNodeXForm<imm, [{ 42 def PowerOf2LO : PatLeaf<(imm), [{ 52 def PowerOf2HI : PatLeaf<(imm), [{ 649 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>, ISA_MIPS3, GPR_64; 652 (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), 653 (LO16 imm:$imm))>, ISA_MIPS3, GPR_64; 847 (CINS64_32 GPR32:$rt, imm:$imm, (immZExt5To31 imm:$imm))>, [all …]
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