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Searched refs:hsub (Results 1 – 12 of 12) sorted by relevance

/freebsd-14.2/sys/arm/nvidia/drm2/
H A Dtegra_fb.c271 int hsub, vsub, i; in tegra_drm_fb_create() local
278 hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format); in tegra_drm_fb_create()
286 width /= hsub; in tegra_drm_fb_create()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td390 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
398 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
437 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
447 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
551 defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;
554 defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;
556 defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
H A DAArch64InstrInfo.td6586 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
6766 hsub), ssub)>;
6770 hsub), ssub)>;
7404 hsub))>;
7409 hsub))>;
7414 hsub))>;
7419 hsub))>;
7424 hsub))>;
7429 hsub))>;
7748 hsub),
[all …]
H A DAArch64SVEInstrInfo.td1952 (LASTB_VPZ_H (PTRUE_H 31), ZPR:$Z1), hsub))>;
3086 (INSERT_SUBREG (nxv8f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3088 (INSERT_SUBREG (nxv4f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3090 (INSERT_SUBREG (nxv2f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3092 (INSERT_SUBREG (nxv8bf16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3299 (f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3301 (f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3303 (f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3305 (bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3307 (bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
[all …]
H A DAArch64RegisterInfo.cpp213 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
215 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
H A DAArch64RegisterInfo.td25 def hsub : SubRegIndex<16>;
331 let SubRegIndices = [hsub] in {
H A DAArch64InstrFormats.td5525 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
5531 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>;
8927 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), V128:$Rm, VectorIndexH:$idx)>;
8956 (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>;
8966 (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>;
9483 (f16 (EXTRACT_SUBREG V64:$Rn, hsub)),
9496 (f16 (EXTRACT_SUBREG V64:$Rn, hsub)),
H A DAArch64InstrInfo.cpp4671 RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
4673 RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
H A DAArch64ISelLowering.cpp4434 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, OpVT, Op); in LowerBITCAST()
9079 SetVecVal(AArch64::hsub); in LowerFCOPYSIGN()
9100 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, BSP); in LowerFCOPYSIGN()
9828 TVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
9830 FVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
9837 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, Ty, Res); in LowerSELECT()
24420 Op = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in ReplaceBITCASTResults()
H A DSVEInstrFormats.td1718 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
1725 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
/freebsd-14.2/sys/dev/drm2/
H A Ddrm_crtc.c2247 int ret, hsub, vsub, num_planes, i; in framebuffer_check() local
2255 hsub = drm_format_horz_chroma_subsampling(r->pixel_format); in framebuffer_check()
2259 if (r->width == 0 || r->width % hsub) { in framebuffer_check()
2270 unsigned int width = r->width / (i != 0 ? hsub : 1); in framebuffer_check()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp641 SubReg = AArch64::hsub; in getSubRegForClass()
3902 return BuildFn(AArch64::hsub); in emitScalarToVector()
4017 ExtractSubReg = AArch64::hsub; in getLaneCopyOpcode()
4388 SubregIdx = AArch64::hsub; in getInsertVecEltOpInfo()