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Searched refs:hasInterval (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveIntervals.h113 if (hasInterval(Reg)) in getInterval()
123 bool hasInterval(Register Reg) const { in hasInterval() function
130 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
146 return hasInterval(Reg) ? getInterval(Reg) : createEmptyInterval(Reg); in getOrCreateEmptyInterval()
H A DLiveStacks.h82 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocBase.cpp147 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
H A DLiveIntervals.cpp159 if (hasInterval(Reg)) in print()
1544 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) { in handleMoveIntoNewBundle()
1672 if (MO.getSubReg() && hasInterval(Reg) && in repairIntervalsInRange()
1676 if (!hasInterval(Reg)) { in repairIntervalsInRange()
H A DRenameIndependentSubregs.cpp395 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
H A DStackSlotColoring.cpp210 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
H A DLiveRangeEdit.cpp430 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
H A DLiveDebugVariables.cpp827 if (!LIS->hasInterval(Reg)) { in handleDebugValue()
1053 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
1129 if (LIS.hasInterval(LocMO.getReg())) { in computeIntervals()
H A DMachineVerifier.cpp2376 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
2515 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
3074 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
H A DInlineSpiller.cpp802 assert(LIS.hasInterval(Reg) && in reMaterializeAll()
H A DMachineBasicBlock.cpp1295 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) in SplitCriticalEdge()
H A DTwoAddressInstructionPass.cpp1996 if (DefIsPartial && LIS->hasInterval(DstReg) && in eliminateRegSequence()
H A DModuloSchedule.cpp345 if (!LIS.hasInterval(ToReg)) in replaceRegUsesAfterLoop()
H A DRegisterCoalescer.cpp3977 if (!LIS->hasInterval(reg)) in lateLiveIntervalUpdate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp229 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
H A DGCNNSAReassign.cpp225 if (!LIS->hasInterval(Reg)) in CheckNSA()
H A DGCNRegPressure.h283 if (!LIS.hasInterval(Reg)) in getLiveRegMap()
H A DGCNRewritePartialRegUses.cpp351 if (!LIS->hasInterval(OldReg)) in updateLiveIntervals()
H A DGCNRegPressure.cpp233 if (!LIS.hasInterval(Reg)) in getLiveRegs()
H A DGCNSchedStrategy.cpp1280 if (!DAG.LIS->hasInterval(Reg)) in collectRematerializableInstructions()
H A DSIRegisterInfo.cpp3156 if (!LIS->hasInterval(Reg)) in findReachingDef()