Home
last modified time | relevance | path

Searched refs:hasFullFP16 (Results 1 – 12 of 12) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSubtarget.h347 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); } in useFPVFMx16()
H A DARMTargetTransformInfo.cpp492 (EltVT == MVT::f16 && ST->hasFullFP16()); in getCastInstrCost()
1684 (EltSize == 16 && ST->hasFullFP16()))) { in getArithmeticReductionCost()
1828 (ValVT.getVectorElementType() == MVT::f16 && ST->hasFullFP16()))) { in getMinMaxReductionCost()
1945 (ST->hasFullFP16() && LT.second == MVT::f16 && MTy == MVT::i32)) in getIntrinsicInstrCost()
1957 (ST->hasFullFP16() && LT.second == MVT::f16) || in getIntrinsicInstrCost()
2018 if (F->getReturnType()->isHalfTy() && !ST->hasFullFP16()) in isLoweredToCall()
2124 if (I.getType()->isHalfTy() && !ST->hasFullFP16()) in maybeLoweredToCall()
H A DARMPredicates.td114 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
H A DARMISelLowering.cpp788 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
800 if (!Subtarget->hasFullFP16()) in ARMTargetLowering()
844 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1088 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1440 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1450 if (Subtarget->hasFullFP16()) in ARMTargetLowering()
1538 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
1572 if (Subtarget->hasFullFP16()) { in ARMTargetLowering()
2168 if (Subtarget->hasFullFP16()) { in MoveToHPR()
2181 if (Subtarget->hasFullFP16()) { in MoveFromHPR()
[all …]
H A DARMISelDAGToDAG.cpp3137 if (VT == MVT::v8i16 && Subtarget->hasFullFP16()) { in tryInsertVectorElt()
3157 if (VT == MVT::v8f16 && Subtarget->hasFullFP16()) { in tryInsertVectorElt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp683 if (ST->hasFullFP16() && in getIntrinsicInstrCost()
692 (ST->hasFullFP16() && LT.second.getScalarType() == MVT::f16)) && in getIntrinsicInstrCost()
2593 if (ST->hasFullFP16()) in getCastInstrCost()
2928 if ((Ty->getScalarType()->isHalfTy() && !ST->hasFullFP16()) || in getArithmeticInstrCost()
3003 (ST->hasFullFP16() && in getCmpSelInstrCost()
3036 if (LT.second == MVT::v4f16 && !ST->hasFullFP16()) in getCmpSelInstrCost()
3545 if (LT.second.getScalarType() == MVT::f16 && !ST->hasFullFP16()) in getMinMaxReductionCost()
H A DAArch64AsmPrinter.cpp1445 FMov.setOpcode(STI->hasFullFP16() ? AArch64::FMOVWHr : AArch64::FMOVWSr); in emitFMov0()
1446 if (!STI->hasFullFP16()) in emitFMov0()
H A DAArch64ISelLowering.cpp677 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
695 if (!Subtarget->hasFullFP16()) { in AArch64TargetLowering()
780 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
789 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
1116 if (Subtarget->hasFullFP16()) { in AArch64TargetLowering()
1247 if (Subtarget->hasFullFP16()) in AArch64TargetLowering()
4029 !Subtarget->hasFullFP16()) { in LowerVectorFP_TO_INT()
4210 if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16()) { in LowerFP_TO_INT_SAT()
14996 !Subtarget->hasFullFP16()) in shouldSinkOperands()
16317 return Subtarget->hasFullFP16(); in isFMAFasterThanFMulAndFAdd()
[all …]
H A DAArch64InstrInfo.td129 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp83 const bool HasFP16 = ST.hasFullFP16(); in AArch64LegalizerInfo()
267 !ST.hasFullFP16(); in AArch64LegalizerInfo()
274 return Query.Types[0] == s16 && !ST.hasFullFP16(); in AArch64LegalizerInfo()
H A DAArch64PostLegalizerLowering.cpp988 if (EltSize == 16 && !ST.hasFullFP16()) in matchLowerVectorFCMP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6013 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTD() local
6031 if (hasFullFP16) { in DecodeVCVTD()
6072 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTQ() local
6090 if (hasFullFP16) { in DecodeVCVTQ()