| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.h | 274 return DAG.getZeroExtendInReg(Op, dl, OldVT); in ZExtPromotedInteger()
288 return DAG.getZeroExtendInReg(Op, DL, OldVT); in SExtOrZExtPromotedInteger()
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| H A D | LegalizeIntegerTypes.cpp | 838 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); in PromoteIntRes_INT_EXTEND()
1414 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT); in PromoteIntRes_FunnelShift()
1467 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT); in PromoteIntRes_VPFunnelShift()
1579 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
2318 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); in PromoteIntOp_ZERO_EXTEND()
4988 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
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| H A D | LegalizeDAG.cpp | 565 Value = DAG.getZeroExtendInReg(Value, dl, StVT); in LegalizeStoreOps()
953 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); in LegalizeLoadOps()
3128 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
3132 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); in ExpandNode()
3133 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
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| H A D | DAGCombiner.cpp | 1582 return DAG.getZeroExtendInReg(NewOp, DL, OldVT); in ZExtPromoteOperand()
13712 Op = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
13724 SDValue And = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
13851 return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType()); in visitZERO_EXTEND()
13861 return DAG.getZeroExtendInReg(DAG.getAnyExtOrTrunc(VsetCC, DL, VT), DL, in visitZERO_EXTEND()
14479 return DAG.getZeroExtendInReg(N0, SDLoc(N), ExtVT); in visitSIGN_EXTEND_INREG()
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| H A D | SelectionDAG.cpp | 1522 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg() function in SelectionDAG
1549 return getZeroExtendInReg(Op, DL, VT); in getPtrExtendInReg()
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| H A D | TargetLowering.cpp | 2360 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT)); in SimplifyDemandedBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 980 Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
990 : DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1074 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1307 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
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| H A D | AMDGPUISelLowering.cpp | 5144 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 10031 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2575 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2683 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy)); in extractVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 989 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2768 FpToInt = DAG.getZeroExtendInReg(FpToInt, DL, MVT::i32); in lowerFP_TO_INT_SAT()
13997 FpToInt = DAG.getZeroExtendInReg(FpToInt, DL, MVT::i32); in performFP_TO_INT_SATCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20237 In = DAG.getZeroExtendInReg(In, DL, DstVT); in truncateVectorWithPACKUS()
24481 StoredVal = DAG.getZeroExtendInReg( in LowerStore()
48011 return DAG.getZeroExtendInReg(Op, DL, NarrowVT); in PromoteMaskArithmetic()
50408 Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1); in combineStore()
52622 Res = DAG.getZeroExtendInReg(Res, dl, N0.getValueType()); in combineExtSetcc()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 18768 : DAG.getZeroExtendInReg(VVT, DL, ExtVT); in PerformMVEExtCombine()
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