Home
last modified time | relevance | path

Searched refs:getXLen (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp71 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress()
72 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress()
215 return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI) in getStackAddress()
336 return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2; in isSupportedArgumentType()
357 return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2; in isSupportedReturnType()
433 unsigned XLenInBytes = Subtarget.getXLen() / 8; in saveVarArgRegisters()
464 Subtarget.getXLen()); in saveVarArgRegisters()
465 const LLT sXLen = LLT::scalar(Subtarget.getXLen()); in saveVarArgRegisters()
H A DRISCVInstructionSelector.cpp241 const unsigned XLen = STI.getXLen(); in selectSHXADDOp()
749 const LLT sXLen = LLT::scalar(STI.getXLen()); in replacePtrWithInt()
762 const LLT sXLen = LLT::scalar(STI.getXLen()); in preISelLower()
771 const LLT sXLen = LLT::scalar(STI.getXLen()); in preISelLower()
794 MIB.addImm(STI.getXLen() - CstVal); in renderImmSubFromXLen()
H A DRISCVLegalizerInfo.cpp41 : STI(ST), XLen(STI.getXLen()), sXLen(LLT::scalar(XLen)) { in RISCVLegalizerInfo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp189 if (Bits >= (ST.getXLen() / 2)) in hasAllNBitUsers()
208 if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm())) in hasAllNBitUsers()
233 if (Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
245 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
H A DRISCVFrameLowering.cpp73 int64_t SlotSize = STI.getXLen() / 8; in emitSCSPrologue()
128 int64_t SlotSize = STI.getXLen() / 8; in emitSCSEpilogue()
519 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); in emitPrologue()
590 (int64_t)STI.getXLen() / 8; in emitPrologue()
592 Offset = FrameIdx * (int64_t)STI.getXLen() / 8; in emitPrologue()
1344 const uint64_t RVCompressLen = STI.getXLen() * 8; in getFirstSPAdjustAmount()
1393 RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16)); in spillCalleeSavedRegisters()
H A DRISCVSubtarget.h167 unsigned getXLen() const { in getXLen() function
H A DRISCVISelDAGToDAG.cpp987 unsigned XLen = Subtarget->getXLen(); in Select()
1016 unsigned XLen = Subtarget->getXLen(); in Select()
1066 unsigned LShAmt = Subtarget->getXLen() - TrailingOnes; in Select()
1100 unsigned LShAmt = Subtarget->getXLen() - ExtSize; in Select()
1145 unsigned XLen = Subtarget->getXLen(); in Select()
1390 unsigned XLen = Subtarget->getXLen(); in Select()
2742 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
2789 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
2971 if (UI.getOperandNo() != 1 || Bits < Log2_32(Subtarget->getXLen())) in hasAllNBitUsers()
2976 if (Bits < Subtarget->getXLen() - User->getConstantOperandVal(1)) in hasAllNBitUsers()
[all …]
H A DRISCVISelDAGToDAG.h89 return selectShiftMask(N, Subtarget->getXLen(), ShAmt); in selectShiftMaskXLen()
H A DRISCVTargetTransformInfo.cpp174 if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() && in getIntImmCostInst()
278 return TypeSize::getFixed(ST->getXLen()); in getRegisterBitWidth()
1244 ST->getXLen() < Val->getScalarSizeInBits()) { in getVectorInstrCost()
H A DRISCVISelLowering.cpp1874 if (BitSize > Subtarget.getXLen()) in shouldConvertConstantLoadToIntImm()
2121 if (Subtarget.getXLen() < VT.getScalarSizeInBits()) { in isFPImmLegal()
7381 int XLenInBytes = Subtarget.getXLen() / 8; in lowerFRAMEADDR()
7404 int XLenInBytes = Subtarget.getXLen() / 8; in lowerRETURNADDR()
11519 unsigned XLen = Subtarget.getXLen(); in ReplaceNodeResults()
12367 if (VT.getSizeInBits() > Subtarget.getXLen()) in combineSelectAndUse()
16461 unsigned XLen = Subtarget.getXLen(); in ComputeNumSignBitsForTargetNode()
16486 assert(Subtarget.getXLen() == 64); in ComputeNumSignBitsForTargetNode()
18119 unsigned XLenInBytes = Subtarget.getXLen() / 8; in LowerFormalArguments()
19438 unsigned XLen = Subtarget.getXLen(); in emitMaskedAtomicRMWIntrinsic()
[all …]
H A DRISCVInstrInfo.cpp492 assert(STI.getXLen() == 64 && "Unexpected GPR size"); in copyPhysReg()
500 assert(STI.getXLen() == 64 && "Unexpected GPR size"); in copyPhysReg()
1297 unsigned XLen = STI.getXLen(); in isBranchOffsetInRange()
H A DRISCVInstrInfoZb.td136 return (unsigned)llvm::popcount(N->getZExtValue()) == Subtarget->getXLen() - 2;
H A DRISCVInstrInfo.td412 uint64_t XLen = Subtarget->getXLen();
457 uint64_t XLen = Subtarget->getXLen();
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/
H A DRISCVISAInfo.h77 unsigned getXLen() const { return XLen; } in getXLen() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Object/
H A DELFObjectFile.cpp311 if (ISAInfo->getXLen() == 32) in getRISCVFeatures()
313 else if (ISAInfo->getXLen() == 64) in getRISCVFeatures()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2743 if (ISAInfo->getXLen() == 32 && isRV64()) in resetToArch()
2745 else if (ISAInfo->getXLen() == 64 && !isRV64()) in resetToArch()
2749 if (ISAInfo->getXLen() == 32) in resetToArch()
2751 else if (ISAInfo->getXLen() == 64) in resetToArch()
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DGnu.cpp1755 addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags); in selectRISCVMultilib()
1756 addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags); in selectRISCVMultilib()
1808 if (MLConfigISAInfo->getXLen() == 32) { in selectRISCVMultilib()
/freebsd-14.2/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp1074 mergedXlen = info.getXLen(); in mergeArch()
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/
H A DDriver.cpp677 unsigned XLen = (*ISAInfo)->getXLen(); in computeTargetTriple()