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Searched refs:getWavefrontSize (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.h77 ST->getWavefrontSize(); in isLaneMaskReg()
H A DAMDGPUSubtarget.cpp328 const unsigned WaveSize = getWavefrontSize(); in getMaxLocalMemSizeWithWaveCount()
352 const unsigned WaveSize = getWavefrontSize(); in getOccupancyWithLocalMemSize()
399 return std::pair(1, getWavefrontSize()); in getDefaultFlatWorkGroupSize()
624 return getWavefrontSize() == 32 ? AMDGPUDwarfFlavour::Wave32 in getAMDGPUDwarfFlavour()
H A DAMDGPUSubtarget.h221 unsigned getWavefrontSize() const { in getWavefrontSize() function
H A DGCNSubtarget.h1425 return getWavefrontSize() == 32; in isWave32()
1429 return getWavefrontSize() == 64; in isWave64()
H A DAMDGPUAtomicOptimizer.cpp571 auto *WaveTy = B.getIntNTy(ST->getWavefrontSize()); in buildScanIteratively()
722 Type *const WaveTy = B.getIntNTy(ST->getWavefrontSize()); in optimizeAtomic()
788 Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1); in optimizeAtomic()
H A DR600ControlFlowFinalizer.cpp82 if (ST->getWavefrontSize() == 64) { in requiresWorkAroundForInst()
93 assert(ST->getWavefrontSize() == 32); in requiresWorkAroundForInst()
H A DAMDGPUAsmPrinter.cpp701 STM.getMaxWaveScratchSize() / STM.getWavefrontSize(); in getSIProgramInfo()
897 ProgInfo.ScratchSize * STM.getWavefrontSize(), 1ULL << ScratchAlignShift); in getSIProgramInfo()
H A DAMDGPUHSAMetadataStreamer.cpp486 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
H A DSIMachineFunctionInfo.cpp406 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPRLane()
H A DSILowerControlFlow.cpp760 const unsigned WavefrontSize = ST.getWavefrontSize(); in lowerInitExec()
H A DAMDGPUInstructionSelector.cpp1361 if (DstTy.getSizeInBits() != STI.getWavefrontSize()) in selectIntrinsicCmp()
1419 const bool IsWave32 = (STI.getWavefrontSize() == 32); in selectBallot()
1423 if (Size != STI.getWavefrontSize() && (!Is64 || !IsWave32)) in selectBallot()
1430 if (Size == STI.getWavefrontSize()) { in selectBallot()
1786 if (WGSize <= STI.getWavefrontSize()) { in selectSBarrier()
H A DAMDGPUCallLowering.cpp1219 if (!ExecArg.Ty->isIntegerTy(ST.getWavefrontSize())) in lowerTailCall()
H A DSIFrameLowering.cpp591 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
H A DSIInstrInfo.td9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
H A DSIISelLowering.cpp3544 if (!RequestedExec.Ty->isIntegerTy(Subtarget->getWavefrontSize())) in LowerCall()
5803 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerICMPIntrinsic()
5833 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerFCMPIntrinsic()
8119 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(), in LowerINTRINSIC_WO_CHAIN()
9290 if (WGSize <= ST.getWavefrontSize()) in LowerINTRINSIC_VOID()
15903 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass in getRegClassFor()
15991 return hasCFUser(V, Visited, Subtarget->getWavefrontSize()); in requiresUniformRegister()
H A DSIRegisterInfo.cpp1473 Offset *= ST.getWavefrontSize(); in buildSpillLoadStore()
H A DAMDGPUISelDAGToDAG.cpp2396 VCMP.getValueType().getSizeInBits() == ST->getWavefrontSize()) { in SelectBRCOND()
H A DSIInstrInfo.cpp7472 unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64 in lowerSelect()
8485 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2; in getScratchRsrcWords23()
H A DAMDGPULegalizerInfo.cpp7072 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize()); in legalizeIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h186 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
H A DAMDGPUBaseInfo.cpp837 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { in getWavefrontSize() function
930 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI)); in getWavesPerWorkGroup()