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Searched refs:getVT (Results 1 – 25 of 46) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcher.h858 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
882 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
907 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
1050 MVT::SimpleValueType getVT(unsigned i) const { in getVT() function
H A DDAGISelMatcherEmitter.cpp762 MVT::SimpleValueType VT = cast<EmitIntegerMatcher>(N)->getVT(); in EmitMatcher()
783 MVT::SimpleValueType VT = cast<EmitStringIntegerMatcher>(N)->getVT(); in EmitMatcher()
803 MVT::SimpleValueType VT = Matcher->getVT(); in EmitMatcher()
966 OS << getEnumName(EN->getVT(i)) << ", "; in EmitMatcher()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp581 MVT MVT::getVT(Type *Ty, bool HandleUnknown){ in getVT() function in MVT
615 getVT(VTy->getElementType(), /*HandleUnknown=*/ false), in getVT()
627 return MVT::getVT(Ty, HandleUnknown); in getEVT()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineValueType.h482 static MVT getVT(Type *Ty, bool HandleUnknown = false);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp287 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp635 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) { in tryShrinkShlLogicImm()
734 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in trySignedBitfieldExtract()
1096 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in Select()
1188 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) { in Select()
1215 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32; in Select()
2683 cast<VTSDNode>(N.getOperand(1))->getVT().getSizeInBits() == Bits) { in selectSExtBits()
H A DRISCVInstrInfo.td1186 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1191 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp558 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1515 : cast<VTSDNode>(N.getOperand(1))->getVT(); in DetectUseSxtw()
1584 if (T->getVT().getSizeInBits() == NumBits) { in keepsLowBits()
1657 return VN->getVT().getSizeInBits() <= 16; in isPositiveHalfWord()
H A DHexagonISelLowering.cpp1060 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSETCC()
2097 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2122 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1194 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps()
3531 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3697 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3977 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
4296 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
4299 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
6748 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
6760 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
6819 assert(!cast<VTSDNode>(N2)->getVT().isVector() && in getNode()
6821 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
[all …]
H A DSelectionDAGDumper.cpp725 OS << ":" << N->getVT(); in print_details()
H A DSelectionDAGISel.cpp2771 if (cast<VTSDNode>(N)->getVT() == VT) in CheckValueType()
2775 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
H A DDAGCombiner.cpp3209 if (TN->getVT() == MVT::i1) { in visitADDLikeCommutative()
4090 if (TN->getVT() == MVT::i1) { in visitSUB()
6585 cast<VTSDNode>(Op.getOperand(1))->getVT() : in SearchForAndLoads()
10950 VT0 = cast<VTSDNode>(Op0.getOperand(1))->getVT(); in foldABSToABD()
10951 VT1 = cast<VTSDNode>(Op1.getOperand(1))->getVT(); in foldABSToABD()
11000 EVT ExtVT = cast<VTSDNode>(N0.getOperand(1))->getVT(); in visitABS()
13402 EVT ExtVT = cast<VTSDNode>(N0->getOperand(1))->getVT(); in visitSIGN_EXTEND()
14090 EVT AssertVT = cast<VTSDNode>(N1)->getVT(); in visitAssertExt()
14200 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); in reduceLoadWidth()
14415 EVT ExtVT = cast<VTSDNode>(N1)->getVT(); in visitSIGN_EXTEND_INREG()
[all …]
H A DTargetLowering.cpp822 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyMultipleUseDemandedBits()
2320 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
2594 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
4701 !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), in SimplifySetCC()
4703 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); in SimplifySetCC()
4806 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
10713 EVT SatVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); in expandFP_TO_INT_SAT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp224 unsigned Width = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in LowerSIGN_EXTEND_INREG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1260 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1273 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()); in getTgtMemIntrinsic()
1296 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1309 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1342 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1353 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
11565 NarrowVT = VTSign->getVT(); in calculateSrcByte()
12231 VTSign->getVT() == MVT::i8) || in performSignExtendInRegCombine()
12233 VTSign->getVT() == MVT::i16))) { in performSignExtendInRegCombine()
12254 VTSign->getVT() == MVT::i8) || in performSignExtendInRegCombine()
[all …]
H A DAMDGPUTargetTransformInfo.cpp891 MVT VT = MVT::getVT(ReadReg->getType()); in isReadRegisterSourceOfDivergence()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4132 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerVectorFP_TO_INT_SAT()
4204 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
14584 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
14595 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
14623 Info.memVT = MVT::getVT(I.getType()); in getTgtMemIntrinsic()
14634 Info.memVT = MVT::getVT(I.getOperand(0)->getType()); in getTgtMemIntrinsic()
14645 Info.memVT = MVT::getVT(Val->getType()); in getTgtMemIntrinsic()
16921 return TypeNode->getVT(); in calculatePreExtendType()
19082 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in isExtendOrShiftOperand()
21906 if ((TypeNode->getVT() == MVT::i8 && width == 8) in checkValueWidth()
[all …]
H A DAArch64ISelDAGToDAG.cpp786 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
2400 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits(); in isBitfieldExtractOpFromSExtInReg()
6837 return cast<VTSDNode>(Root->getOperand(3))->getVT(); in getMemVTFromNode()
6839 return cast<VTSDNode>(Root->getOperand(4))->getVT(); in getMemVTFromNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp984 MVT VT = MVT::getVT(Outs[I].Ty); in checkReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp405 LLT OldLLT(MVT::getVT(CurArgInfo.Ty)); in lowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1904 cast<VTSDNode>(Op.getOperand(1).getNode())->getVT().getSimpleVT(); in LowerSIGN_EXTEND_INREG()
2444 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1005 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
1006 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp501 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); in performANDCombine()
909 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); in performSRACombine()

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