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Searched refs:getSubClassWithSubReg (Results 1 – 20 of 20) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.h69 getSubClassWithSubReg(const TargetRegisterClass *RC,
H A DX86RegisterInfo.cpp85 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in X86RegisterInfo
93 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
102 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); in getMatchingSuperRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h64 getSubClassWithSubReg(const TargetRegisterClass *RC,
H A DAArch64RegisterInfo.cpp210 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in AArch64RegisterInfo
219 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp285 assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg)); in getRegClassWithShiftedSubregs()
H A DAMDGPUInstructionSelector.cpp530 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg); in selectG_EXTRACT()
614 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
836 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg); in selectG_INSERT()
2356 = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); in selectG_TRUNC()
H A DAMDGPUISelDAGToDAG.cpp377 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
H A DSIInstrInfo.cpp6110 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
572 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
H A DFastISel.cpp2194 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h390 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() function
H A DCodeGenTarget.cpp388 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); in getSuperRegForSubReg()
H A DCodeGenRegisters.cpp1054 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx); in getMatchingSubClassWithSubRegs()
1635 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
2329 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
H A DRegisterInfoEmitter.cpp1516 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h649 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp533 if (getSubClassWithSubReg(RC, Idx) != RC) in getCoveringSubRegIndexes()
H A DPeepholeOptimizer.cpp521 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
531 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
H A DMachineInstr.cpp982 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
H A DMachineVerifier.cpp2324 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp806 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in selectTruncOrPtrToInt()
1270 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in emitExtractSubreg()