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Searched refs:getSpillSize (Results 1 – 25 of 45) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
H A DXCoreFrameLowering.cpp579 unsigned Size = TRI.getSpillSize(RC); in processFunctionBeforeFrameFinalized()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp165 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createEhDataRegsFI()
179 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createISRRegFI()
206 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
H A DMipsFrameLowering.cpp127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
H A DMipsSEFrameLowering.cpp897 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
913 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LowerTileCopy.cpp90 unsigned Size = TRI->getSpillSize(X86::TILERegClass); in runOnMachineFunction()
94 Size = TRI->getSpillSize(X86::GR64RegClass); in runOnMachineFunction()
H A DX86FastPreTileConfig.cpp127 unsigned Size = TRI->getSpillSize(RC); in getStackSpaceFor()
H A DX86InstrInfo.cpp4256 switch (STI.getRegisterInfo()->getSpillSize(*RC)) { in getLoadStoreRegOpcode()
4621 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in storeRegToStackSlot()
4624 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in storeRegToStackSlot()
4645 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in loadRegFromStackSlot()
4647 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in loadRegFromStackSlot()
8214 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode()
8325 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
8405 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16); in unfoldMemoryOperand()
8471 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
8541 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp307 assert(TRI->getSpillSize(*RC) == 4 && in storeRegToStackSlot()
335 assert(TRI->getSpillSize(*RC) == 4 && in loadRegFromStackSlot()
H A DARCFrameLowering.cpp442 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), in processFunctionBeforeFrameFinalized()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
H A DHexagonFrameLowering.cpp1669 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset); in assignCalleeSavedSpillSlots()
1681 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
1905 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandStoreVec2()
1952 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandLoadVec2()
2122 unsigned S = HRI.getSpillSize(*RC); in determineCalleeSaves()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DStackMaps.cpp290 Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC), in parseOperand()
376 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg)); in createLiveOutReg()
H A DRegisterScavenging.cpp230 unsigned NeedSize = TRI->getSpillSize(RC); in spill()
H A DTargetInstrInfo.cpp394 Size = TRI->getSpillSize(*RC); in getStackSlotRange()
410 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range"); in getStackSlotRange()
413 Offset = TRI->getSpillSize(*RC) - (Offset + Size); in getStackSlotRange()
H A DVirtRegMap.cpp96 unsigned Size = TRI->getSpillSize(*RC); in createSpillSlot()
H A DFixupStatepointCallerSaved.cpp94 return TRI.getSpillSize(*RC); in getRegisterSize()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp557 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false); in getScavengeFI()
560 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), in getScavengeFI()
H A DSILowerSGPRSpills.cpp237 int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC), in spillCalleeSavedRegs()
H A DSIFrameLowering.cpp81 unsigned Size = TRI->getSpillSize(RC); in getVGPRSpillLaneOrTempRegister()
1346 FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC), in processFunctionBeforeFrameFinalized()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp749 assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) && in storeRegToStackSlot()
767 assert(MFI.getObjectSize(FrameIndex) >= TRI->getSpillSize(*RC) && in loadRegFromStackSlot()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFrameLowering.cpp169 int FI = MFI.CreateStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC), in processFunctionBeforeFrameFinalized()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h292 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp441 unsigned size = TRI->getSpillSize(*RC); in determineCalleeSaves()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp231 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
1043 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()

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